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Searched refs:CSR_WRITE_1 (Results 1 – 2 of 2) sorted by relevance

/titanic_44/usr/src/uts/common/io/yge/
H A Dyge.c368 CSR_WRITE_1(dev, MR_ADDR(port->p_port, GMAC_IRQ_MSK), in yge_mii_notify()
573 CSR_WRITE_1(dev, B0_POWER_CTRL, in yge_phy_power()
589 CSR_WRITE_1(dev, B2_Y2_CLK_GATE, val); in yge_phy_power()
674 CSR_WRITE_1(dev, B2_Y2_CLK_GATE, val); in yge_phy_power()
675 CSR_WRITE_1(dev, B0_POWER_CTRL, in yge_phy_power()
699 CSR_WRITE_1(dev, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); in yge_reset()
706 CSR_WRITE_1(dev, B0_CTST, CS_RST_SET); in yge_reset()
707 CSR_WRITE_1(dev, B0_CTST, CS_RST_CLR); in yge_reset()
710 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_ON); in yge_reset()
714 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_ON); in yge_reset()
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H A Dyge.h1820 #define CSR_WRITE_1(d, reg, v) \ macro
1832 #define CSR_PCI_WRITE_1(d, reg, v) CSR_WRITE_1(d, Y2_CFG_SPC + (reg), (v))