Searched refs:CSR_READ_1 (Results 1 – 2 of 2) sorted by relevance
| /titanic_44/usr/src/uts/common/io/yge/ |
| H A D | yge.c | 542 dev->d_ramsize = CSR_READ_1(dev, B2_E_0) * 4; in yge_setup_rambuffer()
966 CSR_READ_1(dev, B2_MAC_1 + (port->p_port * 8) + i); in yge_init_port()
1226 dev->d_hw_id = CSR_READ_1(dev, B2_CHIP_ID); in yge_attach()
1227 dev->d_hw_rev = (CSR_READ_1(dev, B2_MAC_CFG) >> 4) & 0x0f; in yge_attach()
1248 dev->d_pmd = CSR_READ_1(dev, B2_PMD_TYP); in yge_attach()
1255 if ((CSR_READ_1(dev, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) == in yge_attach()
1257 if (!(CSR_READ_1(dev, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) in yge_attach()
2027 status = CSR_READ_1(dev, MR_ADDR(pnum, GMAC_IRQ_SRC)); in yge_intr_gmac()
2452 (void) CSR_READ_1(dev, MR_ADDR(pnum, GMAC_IRQ_SRC)); in yge_start_port()
2667 (void) CSR_READ_1(dev, RB_ADDR(rxq, RB_CTRL)); in yge_set_rambuffer()
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| H A D | yge.h | 1827 #define CSR_READ_1(d, reg) \ macro
1836 #define CSR_PCI_READ_1(d, reg) CSR_READ_1(d, Y2_CFG_SPC + (reg))
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