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Searched refs:BIT_0 (Results 1 – 21 of 21) sorted by relevance

/titanic_44/usr/src/uts/common/sys/fibre-channel/fca/qlc/
H A Dql_mbx.h166 #define SE_NIC_2 BIT_0
278 #define IDC_FUNC_SRC_MASK (BIT_3 | BIT_2 | BIT_1 | BIT_0)
291 #define IDC_FUNC_0 BIT_0
293 #define IDC_NIC_FUNC (BIT_1 | BIT_0)
302 #define IDC_RIO_MASK (BIT_3 | BIT_2 | BIT_1 | BIT_0)
330 #define IDC_MM_MASK (BIT_3 | BIT_2 | BIT_1 | BIT_0)
443 #define MBX_0 BIT_0
470 #define FO1_AE_ON_LIPF8 BIT_0
488 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0
495 #define FO3_ENABLE_EMERG_IOCB BIT_0
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H A Dql_xioctl.h208 #define FLASH128 BIT_0
227 #define LED_ACTIVE BIT_0
233 #define BEACON_ON BIT_0
239 #define LED_RED BIT_0
298 #define FTYPE_FCODE BIT_0
422 #define QL_AEN_TRACKING_ENABLE BIT_0
H A Dql_api.h160 #define BIT_0 0x1 macro
347 #define QL_N_PORT BIT_0
507 #define ISP_RESET BIT_0 /* ISP soft reset */
536 #define NX_MBX_CMD BIT_0 /* Mailbox command present */
537 #define NX_RISC_INT BIT_0 /* RISC interrupt present */
543 #define NV_CLOCK BIT_0
807 #define VPO_HARD_ASSIGNED_ID BIT_0
1082 #define MFLG_32BIT_ONLY BIT_0
1175 #define SRB_ISP_STARTED BIT_0 /* Command sent to ISP. */
1240 #define LQF_UNTAGGED_PENDING BIT_0
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H A Dql_iocb.h183 #define CF_WR BIT_0
333 #define FCP_RSP_LEN_VALID BIT_0
346 #define SF_GOT_BUS BIT_0
359 #define SF_ACA_Q BIT_0
635 #define CF_CLEAR_ACA BIT_0
660 #define AF_NO_ABTS BIT_0
1425 #define VMF_DO_NOT_UPDATE_FW BIT_0
H A Dql_init.h878 #define LNF_NVRAM_DATA BIT_0 /* get nvram */
/titanic_44/usr/src/uts/common/io/skd/
H A Dskd.h66 #define BIT_0 0x00001 macro
88 #define SKD_ATTACHED BIT_0
110 #define LOW_POWER_LEVEL (BIT_1 | BIT_0)
/titanic_44/usr/src/uts/common/io/fibre-channel/fca/qlc/
H A Dql_init.c346 w16 = (uint16_t)(w16 & ~BIT_0); in ql_pci_sbus_config()
583 nv->node_name[0] = (uint8_t)(nv->node_name[0] & ~BIT_0); in ql_nvram_config()
584 nv->port_name[0] = (uint8_t)(nv->node_name[0] | BIT_0); in ql_nvram_config()
648 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0)); in ql_nvram_config()
651 BIT_7 | BIT_6 | BIT_5 | BIT_2 | BIT_0); in ql_nvram_config()
748 (ip_icb->ip_firmware_options[0] | BIT_2 | BIT_0); in ql_nvram_config()
853 data = (uint16_t)(data | BIT_0); in ql_nvram_request()
1051 nv->node_name[0] = (uint8_t)(nv->node_name[0] & ~BIT_0); in ql_nvram_24xx_config()
1052 nv->port_name[0] = (uint8_t)(nv->node_name[0] | BIT_0); in ql_nvram_24xx_config()
1126 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0)); in ql_nvram_24xx_config()
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H A Dql_mbx.c1073 mcp->mb[10] = BIT_0; in ql_abort_target()
1076 mcp->mb[1] = (uint16_t)(tq->loop_id << 8 | BIT_0); in ql_abort_target()
1776 (pkt->log.io_param[0] & BIT_4 ? 0 : BIT_0); in ql_log_iocb()
3224 mcp->mb[4] = BIT_0; in ql_execute_fw()
3409 mcp->mb[1] = BIT_0; in ql_init_firmware()
4045 if (option & BIT_0) { in ql_iidma_rate()
4179 mcp->mb[2] = BIT_0; in ql_fw_etrace()
H A Dql_isr.c274 if (mbx & BIT_0) { in ql_isr_aif()
1688 if (status & BIT_0) { in ql_response_pkt()
2363 rval |= BIT_0; in ql_status_error()
H A Dql_iocb.c1256 (uint16_t)(BIT_0)); in ql_ip_24xx_iocb()
H A Dql_nx.c1133 if (!(status & BIT_0)) { in ql_8021_wait_flash_done()
H A Dql_api.c997 size = ql_pci_config_get32(ha, PCI_CONF_BASE0) & BIT_0 ? in ql_attach()
1175 if (ha->function_number & BIT_0) { in ql_attach()
2448 firmware_options_1[0] & BIT_0) { in ql_bind_port()
2456 BIT_0) { in ql_bind_port()
11560 if (!(fdata & BIT_0)) { in ql_24xx_write_flash()
13318 BIT_0) { in ql_2200_binary_fw_dump()
16201 ha2->task_daemon_flags, (options & BIT_0 ? "stalled" : in ql_stall_driver()
16203 if (options & BIT_0) { in ql_stall_driver()
/titanic_44/usr/src/cmd/picl/plugins/sun4u/snowbird/envmond/
H A Dpiclsensors.h68 #define LOW_WARNING_BIT(_X) (BIT_0(_X))
H A Dpiclenvmond.h89 #define BIT_0(_X) ((_X) & 0x01) macro
/titanic_44/usr/src/uts/common/io/comstar/port/qlt/
H A Dqlt_regs.h82 #define CHIP_SOFT_RESET BIT_0
109 BIT_3 | BIT_2 | BIT_1 | BIT_0)
H A Dqlt.c1348 BIT_2 | BIT_1 | BIT_0); in qlt_port_online()
1401 mcp->to_fw[1] = (uint16_t)(mcp->to_fw[1] | BIT_0); in qlt_port_online()
1423 mcp->to_fw_mask = BIT_0; in qlt_port_online()
1424 mcp->from_fw_mask = BIT_0 | BIT_1; in qlt_port_online()
1437 mcp->to_fw_mask = BIT_0; in qlt_port_online()
1439 BIT_0; in qlt_port_online()
1516 mcp->to_fw_mask |= BIT_0 | BIT_9; in qlt_get_link_info()
1517 mcp->from_fw_mask |= BIT_0 | BIT_1 | BIT_2 | BIT_3 | BIT_6 | BIT_7; in qlt_get_link_info()
1570 mcp->to_fw_mask |= BIT_0 | BIT_1 | BIT_9 | BIT_10; in qlt_get_link_info()
2483 mcp->to_fw_mask |= BIT_0; in qlt_alloc_mailbox_command()
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/titanic_44/usr/src/uts/common/sys/
H A Dstmf_defines.h31 #define BIT_0 0x1 macro
/titanic_44/usr/src/uts/common/sys/fibre-channel/fca/qlge/
H A Dqlge.h234 #define INIT_SOFTSTATE_ALLOC BIT_0
313 #define NEED_HW_RESET BIT_0 /* need hardware reset */
692 #define LOW_POWER_LEVEL (BIT_1 | BIT_0)
H A Dqlge_hw.h44 #define BIT_0 0x1 macro
520 #define CQ_0_NOT_EMPTY BIT_0
1002 #define INTERRUPTS_ENABLED BIT_0
1581 #define IDC_REQ_DEST_FUNC_0_MASK BIT_0 /* Mailbox 2 */
2315 #define FLASH128 BIT_0
2448 #define FLT_ATTR_READ_ONLY BIT_0
/titanic_44/usr/src/uts/common/io/fibre-channel/fca/fcoei/
H A Dfcoei_eth.c995 (FCOE_B2V_4(src + offset) & BIT_0) ? 1 : 0; in fcoei_fill_els_fpkt_resp()
1096 (FCOE_B2V_1(src + offset) & BIT_0) ? 1 : 0; in fcoei_fill_fcp_resp()
/titanic_44/usr/src/uts/common/io/fibre-channel/fca/qlge/
H A Dqlge_flash.c1162 if ((flash_status & BIT_0 /* WIP */) == 0) in ql_flash_erase_sector()
1201 if ((flash_status & BIT_0 /* WIP */) == 0) in ql_write_flash()