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Searched refs:BITS (Results 1 – 25 of 26) sorted by relevance

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/titanic_44/usr/src/uts/common/io/rtw/
H A Dsa2400reg.h45 #define SA2400_TWI_DATA_MASK BITS(31, 8)
47 #define SA2400_TWI_ADDR_MASK BITS(6, 0)
63 #define SA2400_SYNA_NF_MASK BITS(20, 18)
68 #define SA2400_SYNA_N_MASK BITS(17, 2)
76 #define SA2400_SYNB_R_MASK BITS(21, 12)
77 #define SA2400_SYNB_L_MASK BITS(11, 10) /* lock detect mode */
97 #define SA2400_SYNB_FC_MASK BITS(7, 0)
99 #define SA2400_SYNC_CP_MASK BITS(7, 6) /* charge pump current setting */
110 #define SA2400_SYNC_SM_MASK BITS(5, 3)
114 #define SA2400_SYND_ZERO1_MASK BITS(21, 17) /* always 0 */
[all …]
H A Dmax2820reg.h47 #define MAX2820_TWI_ADDR_MASK BITS(15, 12)
48 #define MAX2820_TWI_DATA_MASK BITS(11, 0)
55 #define MAX2820_TEST_DEFAULT BITS(2, 0) /* Always set to this value. */
115 #define MAX2820_SYNTH_RSVD0 BITS(11, 7) /* reserved */
127 #define MAX2820_SYNTH_R_MASK BITS(5, 0)
134 #define MAX2820_CHANNEL_RSVD BITS(11, 7) /* reserved */
139 #define MAX2820_CHANNEL_CF_MASK BITS(6, 0)
151 #define MAX2820_RECEIVE_2C_MASK BITS(11, 9)
155 #define MAX2820_RECEIVE_1C_MASK BITS(8, 6)
163 #define MAX2820_RECEIVE_DL_MASK BITS(5, 4)
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H A Drtwreg.h54 #define BITS(m, n) ((BIT(MAX((m), (n)) + 1) - 1) ^ (BIT(MIN((m), (n))) - 1)) macro
137 #define RTW_BRSR_MBR8180_MASK BITS(1, 0) /* Maximum Basic Service Rate */
265 #define RTW_TCR_HWVERID_MASK BITS(29, 25)
277 #define RTW_TCR_MXDMA_MASK BITS(23, 21)
297 #define RTW_TCR_LBK_MASK BITS(18, 17)
311 #define RTW_TCR_SRL_MASK BITS(15, 8) /* Short Retry Limit */
312 #define RTW_TCR_LRL_MASK BITS(7, 0) /* Long Retry Limit */
341 #define RTW_RCR_RXFTH_MASK BITS(15, 13)
354 #define RTW_RCR_MXDMA_MASK BITS(10, 8)
430 #define RTW_9346CR_EEM_MASK BITS(7, 6) /* Operating Mode */
[all …]
H A Dsi4136reg.h46 #define SI4126_TWI_DATA_MASK BITS(21, 4)
47 #define SI4126_TWI_ADDR_MASK BITS(3, 0)
53 #define SI4126_MAIN_AUXSEL_MASK BITS(13, 12) /* aux. output pin function */
70 #define SI4126_MAIN_IFDIV_MASK BITS(11, 10)
81 #define SI4126_GAIN_KPI_MASK BITS(5, 4) /* IF phase detector gain */
82 #define SI4126_GAIN_KP2_MASK BITS(3, 2) /* RF2 phase detector gain */
83 #define SI4126_GAIN_KP1_MASK BITS(1, 0) /* RF1 phase detector gain */
H A Drtw.c1003 *addr = MASK_AND_RSHIFT(idr0, BITS(0, 7)); in rtw_identify_sta()
1004 *(addr + 1) = MASK_AND_RSHIFT(idr0, BITS(8, 15)); in rtw_identify_sta()
1005 *(addr + 2) = MASK_AND_RSHIFT(idr0, BITS(16, 23)); in rtw_identify_sta()
1006 *(addr + 3) = MASK_AND_RSHIFT(idr0, BITS(24, 31)); in rtw_identify_sta()
1008 *(addr + 4) = MASK_AND_RSHIFT(idr1, BITS(0, 7)); in rtw_identify_sta()
1009 *(addr + 5) = MASK_AND_RSHIFT(idr1, BITS(8, 15)); in rtw_identify_sta()
/titanic_44/usr/src/head/
H A Dvalues.h50 #define BITS(type) (BITSPERBYTE * (long)sizeof (type)) macro
53 #define HIBITS ((short)(1 << (BITS(short) - 1)))
55 #define HIBITI (1U << (BITS(int) - 1))
56 #define HIBITL (1UL << (BITS(long) - 1))
111 #define DSIGNIF (BITS(double) - _DEXPLEN + _HIDDENBIT - 1)
112 #define FSIGNIF (BITS(float) - _FEXPLEN + _HIDDENBIT - 1)
113 #define DMAXPOWTWO ((double)(1 << (BITS(int) - 2)) * \
114 (1 << (DSIGNIF - BITS(int) + 1)))
/titanic_44/usr/src/lib/libbc/inc/include/
H A Dvalues.h44 #define BITS(type) (BITSPERBYTE * (int)sizeof(type)) macro
47 #define HIBITS ((short)(1 << BITS(short) - 1))
48 #define HIBITI (1U << BITS(int) - 1)
49 #define HIBITL (1UL << BITS(long) - 1)
126 #define DSIGNIF (BITS(double) - _DEXPLEN + _HIDDENBIT - 1)
127 #define FSIGNIF (BITS(float) - _FEXPLEN + _HIDDENBIT - 1)
128 #define DMAXPOWTWO ((double)(1L << BITS(long) - 2) * \
129 (1L << DSIGNIF - BITS(long) + 1))
/titanic_44/usr/src/lib/libcmd/common/
H A Dstty.c99 #define BITS 2 macro
306 { "cr0", BITS, O_FLAG, IG|SS, CRDLY, CR0 },
307 { "cr1", BITS, O_FLAG, US, CRDLY, CR1 },
308 { "cr2", BITS, O_FLAG, US, CRDLY, CR2 },
309 { "cr3", BITS, O_FLAG, US, CRDLY, CR3 },
312 { "nl0", BITS, O_FLAG, IG|US, NLDLY, NL0 },
313 { "nl1", BITS, O_FLAG, US, NLDLY, NL1 },
318 { "tab0", BITS, O_FLAG, IG|SS, TABDLY, TAB0 },
321 { "tab1", BITS, O_FLAG, US, TABDLY, TAB1 },
324 { "tab2", BITS, O_FLAG, US, TABDLY, TAB2 },
[all …]
/titanic_44/usr/src/cmd/compress/
H A Dcompress.c65 #ifndef BITS
66 #define BITS PBITS macro
70 #if BITS == 16
73 #if BITS == 15
76 #if BITS == 14
79 #if BITS == 13
82 #if BITS <= 12
86 #define OUTSTACKSIZE (2<<BITS)
91 #if BITS > 15
134 static int maxbits = BITS; /* user settable max # bits/code */
[all …]
/titanic_44/usr/src/lib/libcpc/i386/
H A Dconf_pentium.c495 #define BITS(v, u, l) \ macro
530 if ((family = BITS(eax, 11, 8)) == 0xf) in cpc_getcpuver()
531 family = BITS(eax, 27, 20); in cpc_getcpuver()
532 if ((model = BITS(eax, 7, 4)) == 0xf) in cpc_getcpuver()
533 model = BITS(eax, 19, 16); in cpc_getcpuver()
548 ver = BITS(edx, 23, 23) ? /* mmx check */ in cpc_getcpuver()
/titanic_44/usr/src/uts/common/zmod/
H A Dinflate.c457 #define BITS(n) \ macro
617 ((BITS(8) << 8) + (hold >> 8)) % 31) {
622 if (BITS(4) != Z_DEFLATED) {
628 len = BITS(4) + 8;
799 state->last = BITS(1);
801 switch (BITS(2)) {
857 state->nlen = BITS(5) + 257;
859 state->ndist = BITS(5) + 1;
861 state->ncode = BITS(4) + 4;
877 state->lens[order[state->have++]] = (unsigned short)BITS(3);
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/titanic_44/usr/src/lib/libast/common/vmalloc/
H A Dvmbest.c155 if(SIZE(node) & BITS)
199 { nextb = (Block_t*)((Vmuchar_t*)DATA(b) + (SIZE(b)&~BITS) );
437 s = SIZE(fp); /**/ASSERT(!(s&BITS));
439 size = (size&~BITS) + s + sizeof(Head_t);
441 else size &= ~BITS;
454 { /**/ASSERT((s&BITS) == 0);
683 /**/ ASSERT((ALIGN%(BITS+1)) == 0 );
703 SIZE(np) = ((s&~BITS) - (size+sizeof(Head_t)))|JUNK|BUSY;
705 SIZE(tp) |= s&BITS;
758 { SIZE(np) &= ~BITS;
[all …]
H A Dvmhdr.h188 #define BITS (07) /* (BUSY|PFREE|JUNK) */ macro
191 #define ISBITS(w) ((w) & BITS)
192 #define CLRBITS(w) ((w) &= ~BITS)
193 #define CPYBITS(w,f) ((w) |= ((f)&BITS) )
431 #define PFDATA(d) ((Head_t*)((Vmuchar_t*)(d)+(SIZE(BLOCK(d))&~BITS)-sizeof(Head_t)) )
455 #define DBBSIZE(d) (SIZE(DBBLOCK(d)) & ~BITS)
H A Dvmstat.c84 { s = SIZE(b)&~BITS;
102 b = (Block_t*)((Vmuchar_t*)DATA(b) + (SIZE(b)&~BITS) );
H A Dvmpool.c83 (s = (SIZE(tp) & ~BITS) + sizeof(Head_t)) >= size )
89 { s = (SIZE(tp) & ~BITS) + sizeof(Head_t);
320 if(seg->size == (s = SIZE(fp)&~BITS))
H A Dvmtrace.c275 else s = SIZE(b)&~BITS;
279 b = (Block_t*)((Vmuchar_t*)DATA(b) + (SIZE(b)&~BITS) );
H A Dvmdebug.c320 b = (Block_t*)((Vmuchar_t*)DATA(b) + (SIZE(b)&~BITS) );
365 b = (Block_t*)((Vmuchar_t*)DATA(b) + (SIZE(b)&~BITS) );
655 next: b = (Block_t*)((Vmuchar_t*)DATA(b) + (SIZE(b)&~BITS));
H A Dvmprivate.c124 { /**/ ASSERT((SIZE(bp)&~BITS) == 0);
H A Dvmlast.c375 if(seg->size == (s = SIZE(fp)&~BITS))
/titanic_44/usr/src/common/mc/mc-amd/
H A Dmcamd_patounum.c45 #define BITS(val, high, low) \ macro
107 dramaddr = BITS(pa, 39, 0) - BITS(base, 39, 24); in iaddr_gen()
118 if ((pailsel = BITS(pa, 14, 12) >> 12 & ilen) != ilsel) { in iaddr_gen()
127 top = BITS(dramaddr, 36, 13) >> 1; in iaddr_gen()
129 top = BITS(dramaddr, 37, 14) >> 2; in iaddr_gen()
131 top = BITS(dramaddr, 38, 15) >> 3; in iaddr_gen()
133 top = BITS(dramaddr, 35, 12); in iaddr_gen()
136 *iaddrp = top | BITS(dramaddr, 11, 0); in iaddr_gen()
H A Dmcamd_rowcol.c413 dramaddr = (BITS(iaddr, 35, 12) << intlvbits) | in iaddr_unnormalize()
414 (mcpp->intlvsel << 12) | BITS(iaddr, 11, 0); in iaddr_unnormalize()
593 BITS(csp.base, maskhi_hi + MC_CSMASK_UNMASKABLE(mcp.rev), in mc_offset_to_pa()
602 BITS(csp.base, maskhi_hi, maskhi_lo) & in mc_offset_to_pa()
603 ~BITS(csp.mask, maskhi_hi, maskhi_lo), in mc_offset_to_pa()
612 BITS(csp.base, masklo_hi, masklo_lo) & in mc_offset_to_pa()
613 ~BITS(csp.mask, masklo_hi, masklo_lo), in mc_offset_to_pa()
H A Dmcamd_rowcol_impl.h50 #define BITS(val, high, low) \ macro
/titanic_44/usr/src/cmd/sgs/rtld/sparcv9/
H A Dboot_elf.s375 #define BITS(v, u, l) (((v) >> (l)) & MASK((u) - (l) + 1)) macro
376 #define H44(v) BITS(v, 43, 22)
377 #define M44(v) BITS(v, 21, 12)
378 #define L44(v) BITS(v, 11, 0)
/titanic_44/usr/src/uts/intel/ia32/os/
H A Dcpc_subr.c182 #define BITS(v, u, l) \ macro
/titanic_44/usr/src/uts/intel/pcbe/
H A Dopteron_pcbe.c488 #define BITS(v, u, l) \ macro

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