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Searched refs:BAR_1 (Results 1 – 6 of 6) sorted by relevance

/titanic_44/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/
H A Dbnxe_context.c285 (volatile void *)((u8_t*)pdev->vars.mapped_bar_addr[BAR_1] + j*LM_DQ_CID_SIZE); in lm_setup_context_pool()
287 context->array[j].cid_resc.reg_handle = pdev->vars.reg_handle[BAR_1]; in lm_setup_context_pool()
649 phy_addr.as_u32.low = (pdev->hw_info.mem_base[BAR_1].as_u32.low) & 0xfffffff0; in lm_allocate_cid()
650 phy_addr.as_u32.high = pdev->hw_info.mem_base[BAR_1].as_u32.high; in lm_allocate_cid()
658 (volatile void *)((u8_t*)pdev->vars.mapped_bar_addr[BAR_1] + cid*LM_DQ_CID_SIZE); in lm_allocate_cid()
659 context->array[cid].cid_resc.reg_handle = pdev->vars.reg_handle[BAR_1]; in lm_allocate_cid()
663 BAR_1, in lm_allocate_cid()
673 (volatile void *)((u8_t*)pdev->vars.mapped_bar_addr[BAR_1] + cid*LM_DQ_CID_SIZE); in lm_allocate_cid()
H A Dlm_devinfo.c390 case BAR_1: in lm_get_bar_offset_direct()
430 case BAR_1: in lm_get_bar_size_direct()
508 if (BAR_1 == i ) in lm_get_bars_info()
1209 max_bar_supported_cons[port] = pdev->hw_info.bar_size[BAR_1] / LM_DQ_CID_SIZE; in lm_get_shmem_license_info()
1267 max_bar_supported_cons[port] = pdev->hw_info.bar_size[BAR_1] / LM_DQ_CID_SIZE; in lm_get_shmem_license_info()
/titanic_44/usr/src/uts/common/io/bnxe/577xx/drivers/common/include/
H A Dmm_uefi.h137 …LM_BAR_WR32_OFFSET((PDEV), BAR_1, (u32_t)((int_ptr_t)((u8_t *)(PDEV)->context_info->array[CID].cid…
138 … (PDEV)->hw_info.mem_base[BAR_1].as_u64 + (DPM_TRIGER_TYPE))), (VAL))
/titanic_44/usr/src/uts/common/io/bnxe/
H A Dbnxe_tx.c971 BnxeCheckAccHandle(pLM->vars.reg_handle[BAR_1]) != DDI_FM_OK) in BnxeTxSendMblk()
/titanic_44/usr/src/grub/grub-0.97/netboot/
H A De1000.c3545 #define BAR_1 1 macro
3580 for(i = BAR_1; i <= BAR_5; i++) {
/titanic_44/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/include/
H A Dlm5710.h450 #define BAR_1 1 //index for BAR1 macro
4283 MM_WRITE_DOORBELL(PDEV,BAR_1,CID,VAL);\
4342 MM_WRITE_DOORBELL(PDEV,BAR_1,CID,VAL);\