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Searched refs:B3_RI_WTO_XA2 (Results 1 – 2 of 2) sorted by relevance

/titanic_44/usr/src/uts/common/io/yge/
H A Dyge.h339 #define B3_RI_WTO_XA2 0x0197 /* 8 bit WR Timeout Queue XA2 (TO7) */ macro
H A Dyge.c808 CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2), RI_TO_53); in yge_reset()