Searched refs:B2_Y2_CLK_GATE (Results 1 – 2 of 2) sorted by relevance
589 CSR_WRITE_1(dev, B2_Y2_CLK_GATE, val); in yge_phy_power()674 CSR_WRITE_1(dev, B2_Y2_CLK_GATE, val); in yge_phy_power()1257 if (!(CSR_READ_1(dev, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) in yge_attach()
290 #define B2_Y2_CLK_GATE 0x011d /* 8 bit Clock Gating (Yukon-2) */ macro