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Searched refs:B0_IMSK (Results 1 – 2 of 2) sorted by relevance

/titanic_44/usr/src/uts/common/io/yge/
H A Dyge.c818 CSR_WRITE_4(dev, B0_IMSK, 0); in yge_reset()
819 (void) CSR_READ_4(dev, B0_IMSK); in yge_reset()
1423 CSR_WRITE_4(dev, B0_IMSK, 0); in yge_detach()
1424 (void) CSR_READ_4(dev, B0_IMSK); in yge_detach()
1727 CSR_WRITE_4(dev, B0_IMSK, 0); in yge_suspend()
1728 (void) CSR_READ_4(dev, B0_IMSK); in yge_suspend()
1780 CSR_WRITE_4(dev, B0_IMSK, 0); in yge_resume()
1781 CSR_WRITE_4(dev, B0_IMSK, Y2_IS_HW_ERR | Y2_IS_STAT_BMU); in yge_resume()
2311 CSR_WRITE_4(dev, B0_IMSK, dev->d_intrmask); in yge_intr()
2312 (void) CSR_READ_4(dev, B0_IMSK); in yge_intr()
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H A Dyge.h260 #define B0_IMSK 0x000c /* 32 bit Interrupt Mask Register */ macro