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Searched refs:A_PL_ENABLE (Results 1 – 12 of 12) sorted by relevance

/titanic_44/usr/src/uts/common/io/chxge/com/
H A Dulp.c47 u32 pl_intr = t1_read_reg_4(ulp->adapter, A_PL_ENABLE); in t1_ulp_intr_enable()
50 t1_write_reg_4(ulp->adapter, A_PL_ENABLE, in t1_ulp_intr_enable()
66 u32 pl_intr = t1_read_reg_4(ulp->adapter, A_PL_ENABLE); in t1_ulp_intr_disable()
68 t1_write_reg_4(ulp->adapter, A_PL_ENABLE, in t1_ulp_intr_disable()
H A Dmc3.c48 u32 en = t1_read_reg_4(mc3->adapter, A_PL_ENABLE); in t1_mc3_intr_enable()
52 t1_write_reg_4(mc3->adapter, A_PL_ENABLE, en | F_PL_INTR_MC3); in t1_mc3_intr_enable()
57 t1_write_reg_4(mc3->adapter, A_PL_ENABLE, in t1_mc3_intr_enable()
65 u32 pl_intr = t1_read_reg_4(mc3->adapter, A_PL_ENABLE); in t1_mc3_intr_disable()
69 t1_write_reg_4(mc3->adapter, A_PL_ENABLE, in t1_mc3_intr_disable()
74 t1_write_reg_4(mc3->adapter, A_PL_ENABLE, in t1_mc3_intr_disable()
H A Dtp.c319 u32 tp_intr = t1_read_reg_4(tp->adapter, A_PL_ENABLE); in t1_tp_intr_enable()
326 t1_write_reg_4(tp->adapter, A_PL_ENABLE, in t1_tp_intr_enable()
333 t1_write_reg_4(tp->adapter, A_PL_ENABLE, in t1_tp_intr_enable()
340 u32 tp_intr = t1_read_reg_4(tp->adapter, A_PL_ENABLE); in t1_tp_intr_disable()
346 t1_write_reg_4(tp->adapter, A_PL_ENABLE, in t1_tp_intr_disable()
352 t1_write_reg_4(tp->adapter, A_PL_ENABLE, in t1_tp_intr_disable()
H A Dmc4.c219 pl_intr = t1_read_reg_4(mc4->adapter, A_PL_ENABLE); in t1_mc4_intr_enable()
220 t1_write_reg_4(mc4->adapter, A_PL_ENABLE, in t1_mc4_intr_enable()
232 pl_intr = t1_read_reg_4(mc4->adapter, A_PL_ENABLE); in t1_mc4_intr_disable()
233 t1_write_reg_4(mc4->adapter, A_PL_ENABLE, in t1_mc4_intr_disable()
H A Dch_mac.c92 mac_intr = t1_read_reg_4(mac->adapter, A_PL_ENABLE); in mac_intr_enable()
94 t1_write_reg_4(mac->adapter, A_PL_ENABLE, mac_intr); in mac_intr_enable()
118 mac_intr = t1_read_reg_4(mac->adapter, A_PL_ENABLE); in mac_intr_disable()
120 t1_write_reg_4(mac->adapter, A_PL_ENABLE, mac_intr); in mac_intr_disable()
H A Despi.c129 u32 enable, pl_intr = t1_read_reg_4(espi->adapter, A_PL_ENABLE); in t1_espi_intr_enable()
140 t1_write_reg_4(espi->adapter, A_PL_ENABLE, pl_intr | F_PL_INTR_ESPI); in t1_espi_intr_enable()
152 u32 pl_intr = t1_read_reg_4(espi->adapter, A_PL_ENABLE); in t1_espi_intr_disable()
155 t1_write_reg_4(espi->adapter, A_PL_ENABLE, pl_intr & ~F_PL_INTR_ESPI); in t1_espi_intr_disable()
H A Dmc5.c520 u32 pl_intr = t1_read_reg_4(mc5->adapter, A_PL_ENABLE); in t1_mc5_intr_enable()
522 t1_write_reg_4(mc5->adapter, A_PL_ENABLE, in t1_mc5_intr_enable()
538 u32 pl_intr = t1_read_reg_4(mc5->adapter, A_PL_ENABLE); in t1_mc5_intr_disable()
540 t1_write_reg_4(mc5->adapter, A_PL_ENABLE, in t1_mc5_intr_disable()
H A Dpm3393.c167 pl_intr = t1_read_reg_4(cmac->adapter, A_PL_ENABLE); in pm3393_interrupt_enable()
169 t1_write_reg_4(cmac->adapter, A_PL_ENABLE, pl_intr); in pm3393_interrupt_enable()
H A Dch_subr.c1012 u32 pl_intr = t1_read_reg_4(adapter, A_PL_ENABLE); in t1_interrupts_enable()
1020 t1_write_reg_4(adapter, A_PL_ENABLE, pl_intr); in t1_interrupts_enable()
1053 t1_write_reg_4(adapter, A_PL_ENABLE, 0); in t1_interrupts_disable()
H A Dregs.h1729 #define A_PL_ENABLE 0xa00 macro
/titanic_44/usr/src/uts/common/io/chxge/
H A Dpe.c1520 enable = t1_read_reg_4(adapter, A_PL_ENABLE); in ext_intr_task()
1521 t1_write_reg_4(adapter, A_PL_ENABLE, enable | F_PL_INTR_EXT); in ext_intr_task()
1531 u32 enable = t1_read_reg_4(adapter, A_PL_ENABLE); in t1_os_elmer0_ext_intr()
1534 t1_write_reg_4(adapter, A_PL_ENABLE, enable & ~F_PL_INTR_EXT); in t1_os_elmer0_ext_intr()
H A Dsge.c507 u32 val = t1_read_reg_4(sge->obj, A_PL_ENABLE); in t1_sge_intr_disable()
509 t1_write_reg_4(sge->obj, A_PL_ENABLE, val & ~SGE_PL_INTR_MASK); in t1_sge_intr_disable()
524 u32 val = t1_read_reg_4(sge->obj, A_PL_ENABLE); in t1_sge_intr_enable()
526 t1_write_reg_4(sge->obj, A_PL_ENABLE, val | SGE_PL_INTR_MASK); in t1_sge_intr_enable()