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Searched refs:A_MC5_DBGI_REQ_ADDR1 (Results 1 – 2 of 2) sorted by relevance

/titanic_44/usr/src/uts/common/io/chxge/com/
H A Dmc5.c183 t1_write_reg_4(adapter, A_MC5_DBGI_REQ_ADDR1, v2); in dbgi_wr_addr3()
432 t1_write_reg_4(adap, A_MC5_DBGI_REQ_ADDR1, 0); in t1_mc5_init()
H A Dregs.h2017 #define A_MC5_DBGI_REQ_ADDR1 0xc80 macro