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Searched refs:A_MC5_DBGI_REQ_ADDR0 (Results 1 – 2 of 2) sorted by relevance

/titanic_44/usr/src/uts/common/io/chxge/com/
H A Dmc5.c182 t1_write_reg_4(adapter, A_MC5_DBGI_REQ_ADDR0, v1); in dbgi_wr_addr3()
208 t1_write_reg_4(adapter, A_MC5_DBGI_REQ_ADDR0, addr_lo); in mc5_write()
480 t1_write_reg_4(adap, A_MC5_DBGI_REQ_ADDR0, start++); in t1_read_mc5_range()
H A Dregs.h2016 #define A_MC5_DBGI_REQ_ADDR0 0xc7c macro