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Searched refs:ASI_IO (Results 1 – 12 of 12) sorted by relevance

/titanic_44/usr/src/uts/sun4u/opl/ml/
H A Ddrmach_asm.s285 lduwa [%o1]ASI_IO, %o2
296 lduha [%o1]ASI_IO, %o2
308 lduha [%o1]ASI_IO, %o2
313 stha %o3, [%o1]ASI_IO
321 stha %o3, [%o1]ASI_IO
350 stha %o3, [%o1]ASI_IO
351 lduha [%o1]ASI_IO, %o2
385 ldxa [%o1]ASI_IO, %o2
389 ldxa [%o1]ASI_IO, %o2
401 lduba [%o1]ASI_IO, %o2
[all …]
/titanic_44/usr/src/uts/sun4/ml/
H A Dsubr_asm.s156 stxa %o1, [%o0]ASI_IO
185 ldxa [%o0]ASI_IO, %o0
229 stwa %o1, [%o0]ASI_IO /* store value via bypass ASI */
243 stha %o1, [%o0]ASI_IO /* store value via bypass ASI */
257 stba %o1, [%o0]ASI_IO /* store byte via bypass ASI */
271 lduwa [%o0]ASI_IO, %o0 /* load value via bypass ASI */
285 lduha [%o0]ASI_IO, %o0 /* load value via bypass ASI */
299 lduba [%o0]ASI_IO, %o0 /* load value via bypass ASI */
/titanic_44/usr/src/uts/sun4u/starfire/ml/
H A Ddrmach.il.cpp146 stwa %o1, [%o0]ASI_IO /* store value via bypass ASI */
160 lduwa [%o0]ASI_IO, %o0 /* load value via bypass ASI */
206 stwa %o2, [%o1]ASI_IO
213 lduwa [%o1]ASI_IO, %g0 /* read back to insure written */
/titanic_44/usr/src/uts/sun4u/cpu/
H A Dus3_jalapeno_asm.s83 ldxa [j_chng_pa]ASI_IO, scr; \
88 ldxa [j_chng_pa]ASI_IO, scr; \
90 stxa scr, [j_chng_pa]ASI_IO; /* clear j_chng[1:0] */ \
92 stxa scr, [j_chng_pa]ASI_IO; /* trigger j_chng */ \
93 ldxa [j_chng_pa]ASI_IO, scr; \
98 ldxa [j_chng_pa]ASI_IO, scr; \
100 stxa scr, [j_chng_pa]ASI_IO; /* deassert j_chng */
123 ldxa [tpa]ASI_IO, scr; \
126 stxa scr, [tpa]ASI_IO;
188 ldxa [scr2]ASI_IO, scr3; \
H A Dcommon_asm.s140 ldxa [scr]ASI_IO, tmp; \
142 ldxa [scr]ASI_IO, out; \
144 ldxa [scr]ASI_IO, scr; \
151 ldxa [addr]ASI_IO, tmp; \
153 ldxa [addr]ASI_IO, high; \
155 ldxa [addr]ASI_IO, low; \
163 stxa %g0, [addr]ASI_IO; \
165 stxa high, [addr]ASI_IO; \
167 stxa low, [addr]ASI_IO
170 ldxa [scr]ASI_IO, out; \
[all …]
/titanic_44/usr/src/uts/sun4u/starcat/ml/
H A Ddrmach_asm.s445 ! ASI_IO to drain/idle the MCs on other Panther procs. The
456 ! via ASI_IO. The address and value fields are assumed to
462 ! via ASI_IO. The address element is assumed to be a 64 bit
496 CHECK_MCU_IDLE(%o1, ASI_IO, %o2, %o3)
521 stxa %o2, [%o1]ASI_IO
522 ldxa [%o1]ASI_IO, %g0 ! read back to insure written
530 stwa %o2, [%o1]ASI_IO
531 lduwa [%o1]ASI_IO, %g0 ! read back to insure written
/titanic_44/usr/src/uts/sun4/sys/
H A Dsun4asi.h47 #define ASI_IO 0x15 /* I/O (uncached, side effect) */ macro
/titanic_44/usr/src/uts/sun4u/io/pci/
H A Dpci_asm.s76 movnz %xcc, ASI_IO, %g1
133 mov ASI_IO, %asi
/titanic_44/usr/src/uts/sun4u/io/px/
H A Dpx_asm_4u.s80 movnz %xcc, ASI_IO, %g1
136 movnz %xcc, ASI_IO, %g1
/titanic_44/usr/src/uts/sun4u/serengeti/ml/
H A Dsbdp.il.cpp161 stwa %o1, [%o0]ASI_IO /* store value via bypass ASI */
175 lduwa [%o0]ASI_IO, %o0 /* load value via bypass ASI */
/titanic_44/usr/src/uts/sun4u/sys/
H A Dmachthread.h75 lduwa [r]ASI_IO, r; \
/titanic_44/usr/src/uts/sun4u/serengeti/io/
H A Dsbdp_mem.c765 *asi = ASI_IO; in mc_get_idle_reg()
1608 *asi = ASI_IO; in mc_get_addr()