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Searched refs:ARRAY_SIZE (Results 1 – 25 of 26) sorted by relevance

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/titanic_44/usr/src/lib/libjedec/common/
H A Dlibjedec.c1274 nents = ARRAY_SIZE(libjedec_vendors_0); in libjedec_vendor_string()
1278 nents = ARRAY_SIZE(libjedec_vendors_1); in libjedec_vendor_string()
1282 nents = ARRAY_SIZE(libjedec_vendors_2); in libjedec_vendor_string()
1286 nents = ARRAY_SIZE(libjedec_vendors_3); in libjedec_vendor_string()
1290 nents = ARRAY_SIZE(libjedec_vendors_4); in libjedec_vendor_string()
1294 nents = ARRAY_SIZE(libjedec_vendors_5); in libjedec_vendor_string()
1298 nents = ARRAY_SIZE(libjedec_vendors_6); in libjedec_vendor_string()
1302 nents = ARRAY_SIZE(libjedec_vendors_7); in libjedec_vendor_string()
1306 nents = ARRAY_SIZE(libjedec_vendors_8); in libjedec_vendor_string()
1310 nents = ARRAY_SIZE(libjedec_vendors_9); in libjedec_vendor_string()
/titanic_44/usr/src/uts/common/io/ib/clients/rdsv3/
H A Dstats.c129 if (avail < ARRAY_SIZE(rdsv3_stat_names)) { in rdsv3_stats_info()
146 ARRAY_SIZE(rdsv3_stat_names)); in rdsv3_stats_info()
147 avail -= ARRAY_SIZE(rdsv3_stat_names); in rdsv3_stats_info()
152 ARRAY_SIZE(rdsv3_stat_names); in rdsv3_stats_info()
H A Dib_stats.c95 if (avail < ARRAY_SIZE(rdsv3_ib_stat_names)) in rdsv3_ib_stats_info_copy()
106 ARRAY_SIZE(rdsv3_ib_stat_names)); in rdsv3_ib_stats_info_copy()
111 return (ARRAY_SIZE(rdsv3_ib_stat_names)); in rdsv3_ib_stats_info_copy()
/titanic_44/usr/src/uts/common/io/arn/
H A Darn_regd.c79 for (i = 0; i < ARRAY_SIZE(allCountries); i++) in ath9k_regd_is_eeprom_valid()
83 for (i = 0; i < ARRAY_SIZE(regDomainPairs); i++) in ath9k_regd_is_eeprom_valid()
131 for (i = 0; i < ARRAY_SIZE(allCountries); i++) { in ath9k_regd_is_ccode_valid()
213 for (i = 0; i < ARRAY_SIZE(allCountries); i++) { in ath9k_regd_find_country()
236 for (i = 0; i < ARRAY_SIZE(regDomainPairs); i++) in ath9k_regd_get_default_country()
241 i = ARRAY_SIZE(regDomainPairs); in ath9k_regd_get_default_country()
251 for (i = 0; i < ARRAY_SIZE(regDomains); i++) { in ath9k_regd_is_valid_reg_domain()
270 for (i = 0; i < ARRAY_SIZE(regDomainPairs); i++) { in ath9k_regd_is_valid_reg_domainPair()
301 (i < ARRAY_SIZE(regDomainPairs)) && (!found); i++) { in ath9k_regd_get_wmode_regdomain()
610 for (i = 0; i < ARRAY_SIZE(j_bandcheck); i++) { in ath9k_regd_japan_check()
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H A Darn_hw.c626 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), in ath9k_hw_init_rxgain_ini()
631 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), in ath9k_hw_init_rxgain_ini()
636 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); in ath9k_hw_init_rxgain_ini()
641 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); in ath9k_hw_init_rxgain_ini()
657 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), in ath9k_hw_init_txgain_ini()
662 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); in ath9k_hw_init_txgain_ini()
667 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); in ath9k_hw_init_txgain_ini()
807 ARRAY_SIZE(ar9285Modes_9285_1_2), 6); in ath9k_hw_do_attach()
810 ARRAY_SIZE(ar9285Common_9285_1_2), 2); in ath9k_hw_do_attach()
815 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), in ath9k_hw_do_attach()
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H A Darn_ani.c33 for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) { in ath9k_hw_get_ani_channel_idx()
59 if (level >= ARRAY_SIZE(ahp->ah_totalSizeDesired)) { in ath9k_hw_ani_control()
64 (unsigned)ARRAY_SIZE(ahp->ah_totalSizeDesired))); in ath9k_hw_ani_control()
167 if (level >= ARRAY_SIZE(firstep)) { in ath9k_hw_ani_control()
171 (unsigned)ARRAY_SIZE(firstep))); in ath9k_hw_ani_control()
189 if (level >= ARRAY_SIZE(cycpwrThr1)) { in ath9k_hw_ani_control()
193 (unsigned)ARRAY_SIZE(cycpwrThr1))); in ath9k_hw_ani_control()
841 for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) { in ath9k_hw_ani_attach()
H A Darn_eeprom.c341 for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) { in ath9k_hw_check_def_eeprom()
1356 numCtlModes = ARRAY_SIZE(ctlModesFor11g) - in ath9k_hw_set_def_power_per_rate_table()
1374 numCtlModes = ARRAY_SIZE(ctlModesFor11g); in ath9k_hw_set_def_power_per_rate_table()
1389 numCtlModes = ARRAY_SIZE(ctlModesFor11a) - in ath9k_hw_set_def_power_per_rate_table()
1403 numCtlModes = ARRAY_SIZE(ctlModesFor11a); in ath9k_hw_set_def_power_per_rate_table()
1489 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); in ath9k_hw_set_def_power_per_rate_table()
1498 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); in ath9k_hw_set_def_power_per_rate_table()
1507 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); in ath9k_hw_set_def_power_per_rate_table()
1527 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); in ath9k_hw_set_def_power_per_rate_table()
1547 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) in ath9k_hw_set_def_power_per_rate_table()
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H A Darn_xmit.c911 if (haltype >= ARRAY_SIZE(sc->sc_haltype2q)) { in arn_tx_get_qnum()
914 haltype, ARRAY_SIZE(sc->sc_haltype2q))); in arn_tx_get_qnum()
1627 if (qnum >= ARRAY_SIZE(sc->sc_txq)) { in arn_txq_setup()
1630 qnum, (unsigned int)ARRAY_SIZE(sc->sc_txq))); in arn_txq_setup()
1680 if (haltype >= ARRAY_SIZE(sc->sc_haltype2q)) { in arn_tx_setup()
1683 haltype, ARRAY_SIZE(sc->sc_haltype2q))); in arn_tx_setup()
1826 ASSERT(cip->ic_cipher < ARRAY_SIZE(ciphermap)); in arn_tx_get_keytype()
H A Darn_main.c1382 for (i = 0; i < ARRAY_SIZE(ath_mac_bb_names); i++) { in arn_mac_bb_name()
1400 for (i = 0; i < ARRAY_SIZE(ath_rf_names); i++) { in arn_rf_name()
1778 for (i = 0; i < ARRAY_SIZE(sc->sc_keymap)/4; i++) { in arn_key_alloc_pair()
1814 for (i = 0; i < ARRAY_SIZE(sc->sc_keymap)/4; i++) { in arn_key_alloc_2pair()
1864 for (i = 0; i < ARRAY_SIZE(sc->sc_keymap); i++) { in arn_key_alloc_single()
3030 for (i = 0; i < ARRAY_SIZE(sc->sc_haltype2q); i++) in arn_attach()
3132 for (i = 0; i < ARRAY_SIZE(sc->sc_bslot); i++) in arn_attach()
H A Darn_calib.c887 for (i = 0; i < ARRAY_SIZE(regList); i++) in ath9k_hw_9285_pa_cal()
951 for (i = 0; i < ARRAY_SIZE(regList); i++) in ath9k_hw_9285_pa_cal()
H A Darn_rc.c977 count = ARRAY_SIZE(nretry_to_per_lookup); in arn_rc_update_per()
992 count = ARRAY_SIZE(nretry_to_per_lookup); in arn_rc_update_per()
H A Darn_core.h50 #define ARRAY_SIZE(x) (sizeof (x) / sizeof (x[0])) macro
/titanic_44/usr/src/cmd/mdb/common/modules/stmf_sbd/
H A Dstmf_sbd.c41 #define ARRAY_SIZE(a) (sizeof (a) / sizeof (*a)) macro
118 stmf_sbd_print_bit_flags(pgr_flag_str, ARRAY_SIZE(pgr_flag_str), in stmf_sbd_print_pgr_info()
131 (pgr->pgr_rsv_type < ARRAY_SIZE(pgr_type_desc)) ? in stmf_sbd_print_pgr_info()
159 (id->protocol_id < ARRAY_SIZE(stmf_protocol_str)) ? in print_scsi_devid_desc()
197 (tpd->protocol_id < ARRAY_SIZE(stmf_protocol_str)) ? in print_transport_id()
366 stmf_sbd_print_bit_flags(key_flag_str, ARRAY_SIZE(key_flag_str), in stmf_sbd_pgr_key_cb()
424 stmf_sbd_print_bit_flags(it_flag_str, ARRAY_SIZE(it_flag_str), in stmf_sbd_it_cb()
/titanic_44/usr/src/uts/common/io/cxgbe/t4nex/
H A Dosdep.h127 #ifndef ARRAY_SIZE
128 #define ARRAY_SIZE(x) (sizeof (x) / sizeof ((x)[0])) macro
H A Dt4_ioctl.c388 for (i = 0; i < ARRAY_SIZE(reg_ranges); i += 2) in regdump()
635 rc = t4_cim_read(sc, A_UP_IBQ_0_RDADDR, ARRAY_SIZE(t4cimqcfg.stat), in read_cim_qcfg()
H A Dt4_nexus.c339 for (i = 0; i < ARRAY_SIZE(sc->cpl_handler); i++) { in t4_devo_attach()
2206 else if (pi->mod_type > 0 && pi->mod_type < ARRAY_SIZE(mod_str)) in t4_os_portmod_changed()
2228 if (opcode >= ARRAY_SIZE(sc->cpl_handler)) in t4_register_cpl_handler()
H A Dt4_sge.c3197 else if (pi->mod_type > 0 && pi->mod_type < ARRAY_SIZE(mod_str)) in update_port_info_kstats()
/titanic_44/usr/src/test/util-tests/tests/libjedec/
H A Dlibjedec_test.c72 for (i = 0; i < ARRAY_SIZE(libjedec_expects); i++) { in main()
/titanic_44/usr/src/uts/common/sys/
H A Dsysmacros.h372 #if !defined(ARRAY_SIZE)
373 #define ARRAY_SIZE(x) (sizeof (x) / sizeof (x[0])) macro
/titanic_44/usr/src/cmd/stat/common/
H A Dacquire.c36 #define ARRAY_SIZE(a) (sizeof (a) / sizeof (*a)) macro
493 for (i = 0; i < ARRAY_SIZE(cpu_states); i++) in cpu_ticks_delta()
/titanic_44/usr/src/grub/grub-0.97/netboot/
H A Dr8169.c76 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) macro
400 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) in rtl8169_init_board()
/titanic_44/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A Dclc.h89 #ifndef ARRAY_SIZE
90 #define ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0])) macro
/titanic_44/usr/src/uts/common/io/cxgbe/common/
H A Dt4_hw.c227 if (delay_idx < ARRAY_SIZE(d) - 1) in t4_wr_mbox_meat()
873 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1); in t4_write_flash()
2326 for (i = 0; i < ARRAY_SIZE(cause_reg); ++i) in t4_intr_clear()
2774 ARRAY_SIZE(val), A_TP_MIB_TCP_OUT_RST); in t4_tp_get_tcp_stats()
2782 ARRAY_SIZE(val), A_TP_MIB_TCP_V6OUT_RST); in t4_tp_get_tcp_stats()
4478 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) in t4_alloc_mac_filt()
4479 ? rem : ARRAY_SIZE(c.u.exact)); in t4_alloc_mac_filt()
/titanic_44/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/
H A Dlm_pf.c558 #ifndef ARRAY_SIZE
559 #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) macro
/titanic_44/usr/src/uts/common/io/bnxe/577xx/common/
H A Dbnxe_clc.c3958 for (i = 0; i < ARRAY_SIZE(reg_set); i++) in elink_warpcore_enable_AN_KR2()
3993 for (i = 0; i < ARRAY_SIZE(reg_set); i++) in elink_disable_kr2()
4047 for (i = 0; i < ARRAY_SIZE(reg_set); i++) in elink_warpcore_enable_AN_KR()
4200 for (i = 0; i < ARRAY_SIZE(reg_set); i++) in elink_warpcore_set_10G_KR()
4606 for (i = 0; i < ARRAY_SIZE(wc_regs); i++) in elink_warpcore_clear_regs()
10536 for (i = 0; i < ARRAY_SIZE(reg_set); i++) in elink_save_848xx_spirom_version()
10609 for (i = 0; i < ARRAY_SIZE(reg_set); i++) in elink_848xx_set_led()

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