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Searched refs:ALLBITS (Results 1 – 2 of 2) sorted by relevance

/titanic_44/usr/src/cmd/mdb/sun4v/modules/ldc/
H A Dldc.c38 #define ALLBITS (u_longlong_t)-1 macro
41 { "raw ", ALLBITS, LDC_MODE_RAW },
42 { "unrel ", ALLBITS, LDC_MODE_UNRELIABLE },
43 { "rel ", ALLBITS, LDC_MODE_RELIABLE },
48 { "init ", ALLBITS, LDC_INIT },
49 { "open ", ALLBITS, LDC_OPEN },
50 { "ready ", ALLBITS, LDC_READY },
51 { "up ", ALLBITS, LDC_UP },
79 { "generic ", ALLBITS, LDC_DEV_GENERIC },
80 { "blk ", ALLBITS, LDC_DEV_BLK },
[all …]
/titanic_44/usr/src/cmd/mdb/intel/modules/amd_opteron/
H A Dao.c28 #define ALLBITS (u_longlong_t)-1 macro
31 { "SyncOnDramAdrParErrEn", ALLBITS, AMD_NB_CFG_SYNCONDRAMADRPARERREN },
32 { "NbMcaToMstCpuEn", ALLBITS, AMD_NB_CFG_NBMCATOMSTCPUEN },
33 { "ReservedBit26", ALLBITS, 0x4000000 },
34 { "DisPciCfgCpuErrRsp", ALLBITS, AMD_NB_CFG_DISPCICFGCPUERRRSP },
35 { "IoRdDatErrEn", ALLBITS, AMD_NB_CFG_IORDDATERREN },
36 { "ChipKillEccEn", ALLBITS, AMD_NB_CFG_CHIPKILLECCEN },
37 { "EccEn", ALLBITS, AMD_NB_CFG_ECCEN },
38 { "SyncOnAnyErrEn", ALLBITS, AMD_NB_CFG_SYNCONANYERREN },
39 { "SyncOnWdogEn", ALLBITS, AMD_NB_CFG_SYNCONWDOGEN },
[all …]