1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_ZCP_HW_H 27 #define _SYS_NXGE_NXGE_ZCP_HW_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <nxge_defs.h> 36 37 /* 38 * Neptune Zerocopy Hardware definitions 39 * Updated to reflect PRM-0.8. 40 */ 41 42 #define ZCP_CONFIG_REG (FZC_ZCP + 0x00000) 43 #define ZCP_INT_STAT_REG (FZC_ZCP + 0x00008) 44 #define ZCP_INT_STAT_TEST_REG (FZC_ZCP + 0x00108) 45 #define ZCP_INT_MASK_REG (FZC_ZCP + 0x00010) 46 47 #define ZCP_BAM4_RE_CTL_REG (FZC_ZCP + 0x00018) 48 #define ZCP_BAM8_RE_CTL_REG (FZC_ZCP + 0x00020) 49 #define ZCP_BAM16_RE_CTL_REG (FZC_ZCP + 0x00028) 50 #define ZCP_BAM32_RE_CTL_REG (FZC_ZCP + 0x00030) 51 52 #define ZCP_DST4_RE_CTL_REG (FZC_ZCP + 0x00038) 53 #define ZCP_DST8_RE_CTL_REG (FZC_ZCP + 0x00040) 54 #define ZCP_DST16_RE_CTL_REG (FZC_ZCP + 0x00048) 55 #define ZCP_DST32_RE_CTL_REG (FZC_ZCP + 0x00050) 56 57 #define ZCP_RAM_DATA_REG (FZC_ZCP + 0x00058) 58 #define ZCP_RAM_DATA0_REG (FZC_ZCP + 0x00058) 59 #define ZCP_RAM_DATA1_REG (FZC_ZCP + 0x00060) 60 #define ZCP_RAM_DATA2_REG (FZC_ZCP + 0x00068) 61 #define ZCP_RAM_DATA3_REG (FZC_ZCP + 0x00070) 62 #define ZCP_RAM_DATA4_REG (FZC_ZCP + 0x00078) 63 #define ZCP_RAM_BE_REG (FZC_ZCP + 0x00080) 64 #define ZCP_RAM_ACC_REG (FZC_ZCP + 0x00088) 65 66 #define ZCP_TRAINING_VECTOR_REG (FZC_ZCP + 0x000C0) 67 #define ZCP_STATE_MACHINE_REG (FZC_ZCP + 0x000C8) 68 #define ZCP_CHK_BIT_DATA_REG (FZC_ZCP + 0x00090) 69 #define ZCP_RESET_CFIFO_REG (FZC_ZCP + 0x00098) 70 #define ZCP_RESET_CFIFO_MASK 0x0F 71 72 #define ZCP_CFIFIO_RESET_WAIT 10 73 #define ZCP_P0_P1_CFIFO_DEPTH 2048 74 #define ZCP_P2_P3_CFIFO_DEPTH 1024 75 #define ZCP_NIU_CFIFO_DEPTH 1024 76 77 typedef union _zcp_reset_cfifo { 78 uint64_t value; 79 struct { 80 #if defined(_BIG_ENDIAN) 81 uint32_t hdw; 82 #endif 83 struct { 84 #if defined(_BIT_FIELDS_HTOL) 85 uint32_t rsrvd:28; 86 uint32_t reset_cfifo3:1; 87 uint32_t reset_cfifo2:1; 88 uint32_t reset_cfifo1:1; 89 uint32_t reset_cfifo0:1; 90 #elif defined(_BIT_FIELDS_LTOH) 91 uint32_t reset_cfifo0:1; 92 uint32_t reset_cfifo1:1; 93 uint32_t reset_cfifo2:1; 94 uint32_t reset_cfifo3:1; 95 uint32_t rsrvd:28; 96 #endif 97 } ldw; 98 #if !defined(_BIG_ENDIAN) 99 uint32_t hdw; 100 #endif 101 } bits; 102 } zcp_reset_cfifo_t, *p_zcp_reset_cfifo_t; 103 104 #define ZCP_CFIFO_ECC_PORT0_REG (FZC_ZCP + 0x000A0) 105 #define ZCP_CFIFO_ECC_PORT1_REG (FZC_ZCP + 0x000A8) 106 #define ZCP_CFIFO_ECC_PORT2_REG (FZC_ZCP + 0x000B0) 107 #define ZCP_CFIFO_ECC_PORT3_REG (FZC_ZCP + 0x000B8) 108 109 /* NOTE: Same as RX_LOG_PAGE_HDL */ 110 #define ZCP_PAGE_HDL_REG (FZC_DMC + 0x20038) 111 112 /* Data Structures */ 113 114 typedef union zcp_config_reg_u { 115 uint64_t value; 116 struct { 117 #if defined(_BIG_ENDIAN) 118 uint32_t hdw; 119 #endif 120 struct { 121 #if defined(_BIT_FIELDS_HTOL) 122 uint32_t rsvd:7; 123 uint32_t mode_32_bit:1; 124 uint32_t debug_sel:8; 125 uint32_t rdma_th:11; 126 uint32_t ecc_chk_dis:1; 127 uint32_t par_chk_dis:1; 128 uint32_t dis_buf_rn:1; 129 uint32_t dis_buf_rq_if:1; 130 uint32_t zc_enable:1; 131 #elif defined(_BIT_FIELDS_LTOH) 132 uint32_t zc_enable:1; 133 uint32_t dis_buf_rq_if:1; 134 uint32_t dis_buf_rn:1; 135 uint32_t par_chk_dis:1; 136 uint32_t ecc_chk_dis:1; 137 uint32_t rdma_th:11; 138 uint32_t debug_sel:8; 139 uint32_t mode_32_bit:1; 140 uint32_t rsvd:7; 141 #endif 142 } ldw; 143 #if !defined(_BIG_ENDIAN) 144 uint32_t hdw; 145 #endif 146 } bits; 147 } zcp_config_reg_t, *zcp_config_reg_pt; 148 149 #define ZCP_DEBUG_SEL_BITS 0xFF 150 #define ZCP_DEBUG_SEL_SHIFT 16 151 #define ZCP_DEBUG_SEL_MASK (ZCP_DEBUG_SEL_BITS << ZCP_DEBUG_SEL_SHIFT) 152 #define RDMA_TH_BITS 0x7FF 153 #define RDMA_TH_SHIFT 5 154 #define RDMA_TH_MASK (RDMA_TH_BITS << RDMA_TH_SHIFT) 155 #define ECC_CHK_DIS (1 << 4) 156 #define PAR_CHK_DIS (1 << 3) 157 #define DIS_BUFF_RN (1 << 2) 158 #define DIS_BUFF_RQ_IF (1 << 1) 159 #define ZC_ENABLE (1 << 0) 160 161 typedef union zcp_int_stat_reg_u { 162 uint64_t value; 163 struct { 164 #if defined(_BIG_ENDIAN) 165 uint32_t hdw; 166 #endif 167 struct { 168 #if defined(_BIT_FIELDS_HTOL) 169 uint32_t rsvd:16; 170 uint32_t rrfifo_urun:1; 171 uint32_t rrfifo_orun:1; 172 uint32_t rsvd1:1; 173 uint32_t rspfifo_uc_err:1; 174 uint32_t buf_overflow:1; 175 uint32_t stat_tbl_perr:1; 176 uint32_t dyn_tbl_perr:1; 177 uint32_t buf_tbl_perr:1; 178 uint32_t tt_tbl_perr:1; 179 uint32_t rsp_tt_index_err:1; 180 uint32_t slv_tt_index_err:1; 181 uint32_t zcp_tt_index_err:1; 182 uint32_t cfifo_ecc3:1; 183 uint32_t cfifo_ecc2:1; 184 uint32_t cfifo_ecc1:1; 185 uint32_t cfifo_ecc0:1; 186 #elif defined(_BIT_FIELDS_LTOH) 187 uint32_t cfifo_ecc0:1; 188 uint32_t cfifo_ecc1:1; 189 uint32_t cfifo_ecc2:1; 190 uint32_t cfifo_ecc3:1; 191 uint32_t zcp_tt_index_err:1; 192 uint32_t slv_tt_index_err:1; 193 uint32_t rsp_tt_index_err:1; 194 uint32_t tt_tbl_perr:1; 195 uint32_t buf_tbl_perr:1; 196 uint32_t dyn_tbl_perr:1; 197 uint32_t stat_tbl_perr:1; 198 uint32_t buf_overflow:1; 199 uint32_t rspfifo_uc_err:1; 200 uint32_t rsvd1:1; 201 uint32_t rrfifo_orun:1; 202 uint32_t rrfifo_urun:1; 203 uint32_t rsvd:16; 204 #endif 205 } ldw; 206 #if !defined(_BIG_ENDIAN) 207 uint32_t hdw; 208 #endif 209 } bits; 210 } zcp_int_stat_reg_t, *zcp_int_stat_reg_pt, zcp_int_mask_reg_t, 211 *zcp_int_mask_reg_pt; 212 213 #define RRFIFO_UNDERRUN (1 << 15) 214 #define RRFIFO_OVERRUN (1 << 14) 215 #define RSPFIFO_UNCORR_ERR (1 << 12) 216 #define BUFFER_OVERFLOW (1 << 11) 217 #define STAT_TBL_PERR (1 << 10) 218 #define BUF_DYN_TBL_PERR (1 << 9) 219 #define BUF_TBL_PERR (1 << 8) 220 #define TT_PROGRAM_ERR (1 << 7) 221 #define RSP_TT_INDEX_ERR (1 << 6) 222 #define SLV_TT_INDEX_ERR (1 << 5) 223 #define ZCP_TT_INDEX_ERR (1 << 4) 224 #define CFIFO_ECC3 (1 << 3) 225 #define CFIFO_ECC0 (1 << 0) 226 #define CFIFO_ECC2 (1 << 2) 227 #define CFIFO_ECC1 (1 << 1) 228 229 typedef union zcp_bam_region_reg_u { 230 uint64_t value; 231 struct { 232 #if defined(_BIG_ENDIAN) 233 uint32_t hdw; 234 #endif 235 struct { 236 #if defined(_BIT_FIELDS_HTOL) 237 uint32_t loj:1; 238 uint32_t range_chk_en:1; 239 uint32_t last_zcfid:10; 240 uint32_t first_zcfid:10; 241 uint32_t offset:10; 242 #elif defined(_BIT_FIELDS_LTOH) 243 uint32_t offset:10; 244 uint32_t first_zcfid:10; 245 uint32_t last_zcfid:10; 246 uint32_t range_chk_en:1; 247 uint32_t loj:1; 248 #endif 249 } ldw; 250 #if !defined(_BIG_ENDIAN) 251 uint32_t hdw; 252 #endif 253 } bits; 254 } zcp_bam_region_reg_t, *zcp_bam_region_reg_pt; 255 256 typedef union zcp_dst_region_reg_u { 257 uint64_t value; 258 struct { 259 #if defined(_BIG_ENDIAN) 260 uint32_t hdw; 261 #endif 262 struct { 263 #if defined(_BIT_FIELDS_HTOL) 264 uint32_t rsvd:22; 265 uint32_t ds_offset:10; 266 #elif defined(_BIT_FIELDS_LTOH) 267 uint32_t rsvd:22; 268 uint32_t ds_offset:10; 269 #endif 270 } ldw; 271 #if !defined(_BIG_ENDIAN) 272 uint32_t hdw; 273 #endif 274 } bits; 275 } zcp_dst_region_reg_t, *zcp_dst_region_reg_pt; 276 277 typedef enum tbuf_size_e { 278 TBUF_4K = 0, 279 TBUF_8K, 280 TBUF_16K, 281 TBUF_32K, 282 TBUF_64K, 283 TBUF_128K, 284 TBUF_256K, 285 TBUF_512K, 286 TBUF_1M, 287 TBUF_2M, 288 TBUF_4M, 289 TBUF_8M 290 } tbuf_size_t; 291 292 typedef enum tbuf_num_e { 293 TBUF_NUM_4 = 0, 294 TBUF_NUM_8, 295 TBUF_NUM_16, 296 TBUF_NUM_32 297 } tbuf_num_t; 298 299 typedef enum tmode_e { 300 TMODE_BASIC = 0, 301 TMODE_AUTO_UNMAP = 1, 302 TMODE_AUTO_ADV = 3 303 } tmode_t; 304 305 typedef struct tte_sflow_attr_s { 306 union { 307 uint64_t value; 308 struct { 309 #if defined(_BIG_ENDIAN) 310 uint32_t hdw; 311 #endif 312 struct { 313 #if defined(_BIT_FIELDS_HTOL) 314 uint32_t ulp_end:18; 315 uint32_t num_buf:2; 316 uint32_t buf_size:4; 317 uint32_t rdc_tbl_offset:8; 318 #elif defined(_BIT_FIELDS_LTOH) 319 uint32_t rdc_tbl_offset:8; 320 uint32_t buf_size:4; 321 uint32_t num_buf:2; 322 uint32_t ulp_end:18; 323 #endif 324 } ldw; 325 #if !defined(_BIG_ENDIAN) 326 uint32_t hdw; 327 #endif 328 } bits; 329 } qw0; 330 331 union { 332 uint64_t value; 333 struct { 334 #if defined(_BIG_ENDIAN) 335 uint32_t hdw; 336 #endif 337 struct { 338 #if defined(_BIT_FIELDS_HTOL) 339 uint32_t ring_base:12; 340 uint32_t skip:1; 341 uint32_t rsvd:1; 342 uint32_t tmode:2; 343 uint32_t unmap_all_en:1; 344 uint32_t ulp_end_en:1; 345 uint32_t ulp_end:14; 346 #elif defined(_BIT_FIELDS_LTOH) 347 uint32_t ulp_end:14; 348 uint32_t ulp_end_en:1; 349 uint32_t unmap_all_en:1; 350 uint32_t tmode:2; 351 uint32_t rsvd:1; 352 uint32_t skip:1; 353 uint32_t ring_base:12; 354 #endif 355 } ldw; 356 #if !defined(_BIG_ENDIAN) 357 uint32_t hdw; 358 #endif 359 } bits; 360 } qw1; 361 362 union { 363 uint64_t value; 364 struct { 365 #if defined(_BIG_ENDIAN) 366 uint32_t hdw; 367 #endif 368 struct { 369 #if defined(_BIT_FIELDS_HTOL) 370 uint32_t busy:1; 371 uint32_t ring_size:4; 372 uint32_t ring_base:27; 373 #elif defined(_BIT_FIELDS_LTOH) 374 uint32_t ring_base:27; 375 uint32_t ring_size:4; 376 uint32_t busy:1; 377 #endif 378 } ldw; 379 #if !defined(_BIG_ENDIAN) 380 uint32_t hdw; 381 #endif 382 } bits; 383 } qw2; 384 385 union { 386 uint64_t value; 387 struct { 388 #if defined(_BIG_ENDIAN) 389 uint32_t hdw; 390 #endif 391 struct { 392 #if defined(_BIT_FIELDS_HTOL) 393 uint32_t rsvd:16; 394 uint32_t toq:16; 395 #elif defined(_BIT_FIELDS_LTOH) 396 uint32_t toq:16; 397 uint32_t rsvd:16; 398 #endif 399 } ldw; 400 #if !defined(_BIG_ENDIAN) 401 uint32_t hdw; 402 #endif 403 } bits; 404 } qw3; 405 406 union { 407 uint64_t value; 408 struct { 409 #if defined(_BIG_ENDIAN) 410 uint32_t hdw; 411 #endif 412 struct { 413 #if defined(_BIT_FIELDS_HTOL) 414 uint32_t rsvd:28; 415 uint32_t dat4:4; 416 #elif defined(_BIT_FIELDS_LTOH) 417 uint32_t dat4:4; 418 uint32_t rsvd:28; 419 #endif 420 } ldw; 421 #if !defined(_BIG_ENDIAN) 422 uint32_t hdw; 423 #endif 424 } bits; 425 } qw4; 426 427 } tte_sflow_attr_t, *tte_sflow_attr_pt; 428 429 #define TTE_RDC_TBL_SFLOW_BITS_EN 0x0001 430 #define TTE_BUF_SIZE_BITS_EN 0x0002 431 #define TTE_NUM_BUF_BITS_EN 0x0002 432 #define TTE_ULP_END_BITS_EN 0x003E 433 #define TTE_ULP_END_EN_BITS_EN 0x0020 434 #define TTE_UNMAP_ALL_BITS_EN 0x0020 435 #define TTE_TMODE_BITS_EN 0x0040 436 #define TTE_SKIP_BITS_EN 0x0040 437 #define TTE_RING_BASE_ADDR_BITS_EN 0x0FC0 438 #define TTE_RING_SIZE_BITS_EN 0x0800 439 #define TTE_BUSY_BITS_EN 0x0800 440 #define TTE_TOQ_BITS_EN 0x3000 441 442 #define TTE_MAPPED_IN_BITS_EN 0x0000F 443 #define TTE_ANCHOR_SEQ_BITS_EN 0x000F0 444 #define TTE_ANCHOR_OFFSET_BITS_EN 0x00700 445 #define TTE_ANCHOR_BUFFER_BITS_EN 0x00800 446 #define TTE_ANCHOR_BUF_FLAG_BITS_EN 0x00800 447 #define TTE_UNMAP_ON_LEFT_BITS_EN 0x00800 448 #define TTE_ULP_END_REACHED_BITS_EN 0x00800 449 #define TTE_ERR_STAT_BITS_EN 0x01000 450 #define TTE_WR_PTR_BITS_EN 0x01000 451 #define TTE_HOQ_BITS_EN 0x0E000 452 #define TTE_PREFETCH_ON_BITS_EN 0x08000 453 454 typedef enum tring_size_e { 455 TRING_SIZE_8 = 0, 456 TRING_SIZE_16, 457 TRING_SIZE_32, 458 TRING_SIZE_64, 459 TRING_SIZE_128, 460 TRING_SIZE_256, 461 TRING_SIZE_512, 462 TRING_SIZE_1K, 463 TRING_SIZE_2K, 464 TRING_SIZE_4K, 465 TRING_SIZE_8K, 466 TRING_SIZE_16K, 467 TRING_SIZE_32K 468 } tring_size_t; 469 470 typedef struct tte_dflow_attr_s { 471 union { 472 uint64_t value; 473 struct { 474 #if defined(_BIG_ENDIAN) 475 uint32_t hdw; 476 #endif 477 struct { 478 #if defined(_BIT_FIELDS_HTOL) 479 uint32_t mapped_in; 480 #elif defined(_BIT_FIELDS_LTOH) 481 uint32_t mapped_in; 482 #endif 483 } ldw; 484 #if !defined(_BIG_ENDIAN) 485 uint32_t hdw; 486 #endif 487 } bits; 488 } qw0; 489 490 union { 491 uint64_t value; 492 struct { 493 #if defined(_BIG_ENDIAN) 494 uint32_t hdw; 495 #endif 496 struct { 497 #if defined(_BIT_FIELDS_HTOL) 498 uint32_t anchor_seq; 499 #elif defined(_BIT_FIELDS_LTOH) 500 uint32_t anchor_seq; 501 #endif 502 } ldw; 503 #if !defined(_BIG_ENDIAN) 504 uint32_t hdw; 505 #endif 506 } bits; 507 } qw1; 508 509 union { 510 uint64_t value; 511 struct { 512 #if defined(_BIG_ENDIAN) 513 uint32_t hdw; 514 #endif 515 struct { 516 #if defined(_BIT_FIELDS_HTOL) 517 uint32_t ulp_end_reached; 518 uint32_t unmap_on_left; 519 uint32_t anchor_buf_flag; 520 uint32_t anchor_buf:5; 521 uint32_t anchor_offset:24; 522 #elif defined(_BIT_FIELDS_LTOH) 523 uint32_t anchor_offset:24; 524 uint32_t anchor_buf:5; 525 uint32_t anchor_buf_flag; 526 uint32_t unmap_on_left; 527 uint32_t ulp_end_reached; 528 #endif 529 } ldw; 530 #if !defined(_BIG_ENDIAN) 531 uint32_t hdw; 532 #endif 533 } bits; 534 } qw2; 535 536 union { 537 uint64_t value; 538 struct { 539 #if defined(_BIG_ENDIAN) 540 uint32_t hdw; 541 #endif 542 struct { 543 #if defined(_BIT_FIELDS_HTOL) 544 uint32_t rsvd1:1; 545 uint32_t prefetch_on:1; 546 uint32_t hoq:16; 547 uint32_t rsvd:6; 548 uint32_t wr_ptr:6; 549 uint32_t err_stat:2; 550 #elif defined(_BIT_FIELDS_LTOH) 551 uint32_t err_stat:2; 552 uint32_t wr_ptr:6; 553 uint32_t rsvd:6; 554 uint32_t hoq:16; 555 uint32_t prefetch_on:1; 556 uint32_t rsvd1:1; 557 #endif 558 } ldw; 559 #if !defined(_BIG_ENDIAN) 560 uint32_t hdw; 561 #endif 562 } bits; 563 } qw3; 564 565 union { 566 uint64_t value; 567 struct { 568 #if defined(_BIG_ENDIAN) 569 uint32_t hdw; 570 #endif 571 struct { 572 #if defined(_BIT_FIELDS_HTOL) 573 uint32_t rsvd:28; 574 uint32_t dat4:4; 575 #elif defined(_BIT_FIELDS_LTOH) 576 uint32_t dat4:4; 577 uint32_t rsvd:28; 578 #endif 579 } ldw; 580 #if !defined(_BIG_ENDIAN) 581 uint32_t hdw; 582 #endif 583 } bits; 584 } qw4; 585 586 } tte_dflow_attr_t, *tte_dflow_attr_pt; 587 588 #define MAX_BAM_BANKS 8 589 590 typedef struct zcp_ram_unit_s { 591 uint32_t w0; 592 uint32_t w1; 593 uint32_t w2; 594 uint32_t w3; 595 uint32_t w4; 596 } zcp_ram_unit_t; 597 598 typedef enum dmaw_type_e { 599 DMAW_NO_CROSS_BUF = 0, 600 DMAW_IP_CROSS_BUF_2, 601 DMAW_IP_CROSS_BUF_3, 602 DMAW_IP_CROSS_BUF_4 603 } dmaw_type_t; 604 605 typedef union zcp_ram_data_u { 606 tte_sflow_attr_t sentry; 607 tte_dflow_attr_t dentry; 608 } zcp_ram_data_t, *zcp_ram_data_pt; 609 610 typedef union zcp_ram_access_u { 611 uint64_t value; 612 struct { 613 #if defined(_BIG_ENDIAN) 614 uint32_t hdw; 615 #endif 616 struct { 617 #if defined(_BIT_FIELDS_HTOL) 618 uint32_t busy:1; 619 uint32_t rdwr:1; 620 uint32_t rsvd:1; 621 uint32_t zcfid:12; 622 uint32_t ram_sel:5; 623 uint32_t cfifo:12; 624 #elif defined(_BIT_FIELDS_LTOH) 625 uint32_t cfifo:12; 626 uint32_t ram_sel:5; 627 uint32_t zcfid:12; 628 uint32_t rsvd:1; 629 uint32_t rdwr:1; 630 uint32_t busy:1; 631 #endif 632 } ldw; 633 #if !defined(_BIG_ENDIAN) 634 uint32_t hdw; 635 #endif 636 } bits; 637 } zcp_ram_access_t, *zcp_ram_access_pt; 638 639 #define ZCP_RAM_WR 0 640 #define ZCP_RAM_RD 1 641 #define ZCP_RAM_SEL_BAM0 0 642 #define ZCP_RAM_SEL_BAM1 0x1 643 #define ZCP_RAM_SEL_BAM2 0x2 644 #define ZCP_RAM_SEL_BAM3 0x3 645 #define ZCP_RAM_SEL_BAM4 0x4 646 #define ZCP_RAM_SEL_BAM5 0x5 647 #define ZCP_RAM_SEL_BAM6 0x6 648 #define ZCP_RAM_SEL_BAM7 0x7 649 #define ZCP_RAM_SEL_TT_STATIC 0x8 650 #define ZCP_RAM_SEL_TT_DYNAMIC 0x9 651 #define ZCP_RAM_SEL_CFIFO0 0x10 652 #define ZCP_RAM_SEL_CFIFO1 0x11 653 #define ZCP_RAM_SEL_CFIFO2 0x12 654 #define ZCP_RAM_SEL_CFIFO3 0x13 655 656 typedef union zcp_ram_benable_u { 657 uint64_t value; 658 struct { 659 #if defined(_BIG_ENDIAN) 660 uint32_t hdw; 661 #endif 662 struct { 663 #if defined(_BIT_FIELDS_HTOL) 664 uint32_t rsvd:15; 665 uint32_t be:17; 666 #elif defined(_BIT_FIELDS_LTOH) 667 uint32_t be:17; 668 uint32_t rsvd:15; 669 #endif 670 } ldw; 671 #if !defined(_BIG_ENDIAN) 672 uint32_t hdw; 673 #endif 674 } bits; 675 } zcp_ram_benable_t, *zcp_ram_benable_pt; 676 677 typedef union zcp_training_vector_u { 678 uint64_t value; 679 struct { 680 #if defined(_BIG_ENDIAN) 681 uint32_t hdw; 682 #endif 683 struct { 684 #if defined(_BIT_FIELDS_HTOL) 685 uint32_t train_vec; 686 #elif defined(_BIT_FIELDS_LTOH) 687 uint32_t train_vec; 688 #endif 689 } ldw; 690 #if !defined(_BIG_ENDIAN) 691 uint32_t hdw; 692 #endif 693 } bits; 694 } zcp_training_vector_t, *zcp_training_vector_pt; 695 696 typedef union zcp_state_machine_u { 697 uint64_t value; 698 struct { 699 #if defined(_BIG_ENDIAN) 700 uint32_t hdw; 701 #endif 702 struct { 703 #if defined(_BIT_FIELDS_HTOL) 704 uint32_t state; 705 #elif defined(_BIT_FIELDS_LTOH) 706 uint32_t state; 707 #endif 708 } ldw; 709 #if !defined(_BIG_ENDIAN) 710 uint32_t hdw; 711 #endif 712 } bits; 713 } zcp_state_machine_t, *zcp_state_machine_pt; 714 715 typedef struct zcp_hdr_s { 716 uint16_t zflowid; 717 uint16_t tcp_hdr_len; 718 uint16_t tcp_payld_len; 719 uint16_t head_of_que; 720 uint32_t first_b_offset; 721 boolean_t reach_buf_end; 722 dmaw_type_t dmaw_type; 723 uint8_t win_buf_offset; 724 } zcp_hdr_t; 725 726 typedef union _zcp_ecc_ctrl { 727 uint64_t value; 728 729 struct { 730 #if defined(_BIG_ENDIAN) 731 uint32_t w1; 732 #endif 733 struct { 734 #if defined(_BIT_FIELDS_HTOL) 735 uint32_t dis_dbl : 1; 736 uint32_t res3 : 13; 737 uint32_t cor_dbl : 1; 738 uint32_t cor_sng : 1; 739 uint32_t res2 : 5; 740 uint32_t cor_all : 1; 741 uint32_t res1 : 7; 742 uint32_t cor_lst : 1; 743 uint32_t cor_snd : 1; 744 uint32_t cor_fst : 1; 745 #elif defined(_BIT_FIELDS_LTOH) 746 uint32_t cor_fst : 1; 747 uint32_t cor_snd : 1; 748 uint32_t cor_lst : 1; 749 uint32_t res1 : 7; 750 uint32_t cor_all : 1; 751 uint32_t res2 : 5; 752 uint32_t cor_sng : 1; 753 uint32_t cor_dbl : 1; 754 uint32_t res3 : 13; 755 uint32_t dis_dbl : 1; 756 #else 757 #error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined 758 #endif 759 } w0; 760 761 #if !defined(_BIG_ENDIAN) 762 uint32_t w1; 763 #endif 764 } bits; 765 } zcp_ecc_ctrl_t; 766 767 #ifdef __cplusplus 768 } 769 #endif 770 771 #endif /* _SYS_NXGE_NXGE_ZCP_HW_H */ 772