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Searched refs:val_p (Results 1 – 22 of 22) sorted by relevance

/titanic_41/usr/src/uts/common/sys/1394/targets/dcam1394/
H A Ddcam_param.h54 uint_t subparam, uint_t *val_p);
59 uint_t feature_elm_inq_reg_offs, uint_t subparam, uint_t *val_p);
63 int param_cap_power_ctrl_get(dcam_state_t *softc_p, uint_t *val_p);
65 uint_t *val_p);
67 uint_t subparam, uint_t *val_p);
68 int param_power_get(dcam_state_t *softc_p, uint_t *val_p);
70 int param_vid_mode_get(dcam_state_t *softc_p, uint_t *val_p);
72 int param_frame_rate_get(dcam_state_t *softc_p, uint_t *val_p);
74 int param_ring_buff_capacity_get(dcam_state_t *softc_p, uint_t *val_p);
77 uint_t *val_p);
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/titanic_41/usr/src/uts/common/io/1394/targets/dcam1394/
H A Ddcam_param.c437 uint_t *val_p) in dcam1394_param_get() argument
444 err = param_cap_power_ctrl_get(softc_p, val_p); in dcam1394_param_get()
448 err = param_cap_vid_mode_get(softc_p, subparam, val_p); in dcam1394_param_get()
457 err = param_cap_frame_rate_get(softc_p, param, subparam, val_p); in dcam1394_param_get()
461 err = param_power_get(softc_p, val_p); in dcam1394_param_get()
465 err = param_vid_mode_get(softc_p, val_p); in dcam1394_param_get()
469 err = param_frame_rate_get(softc_p, val_p); in dcam1394_param_get()
473 err = param_ring_buff_capacity_get(softc_p, val_p); in dcam1394_param_get()
477 err = param_ring_buff_num_frames_ready_get(softc_p, val_p); in dcam1394_param_get()
481 err = param_ring_buff_read_ptr_incr_get(softc_p, val_p); in dcam1394_param_get()
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/titanic_41/usr/src/uts/common/io/hxge/
H A Dhxge_common_impl.h172 #define HXGE_MEM_PIO_READ64(hpi_handle, val_p) { \ argument
174 *(val_p) = ddi_get64(HPI_REGH(hpi_handle), \
184 #define HXGE_REG_RD64(handle, offset, val_p) { \ argument
186 *(val_p) = HXGE_HPI_PIO_READ64(handle, offset); \
189 #define HXGE_REG_RD32(handle, offset, val_p) { \ argument
191 *(val_p) = HXGE_HPI_PIO_READ32(handle, offset); \
203 #define HXGE_MEM_PIO_READ64(hpi_handle, val_p) { \ argument
204 *(val_p) = ddi_get64(HPI_REGH(hpi_handle), \
210 #define HXGE_REG_RD64(handle, offset, val_p) { \ argument
211 *(val_p) = HXGE_HPI_PIO_READ64(handle, offset); \
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H A Dhxge_pfc.h52 #define REG_PIO_READ64(handle, offset, val_p) \ argument
53 HXGE_REG_RD64((handle), (offset), (val_p))
65 #define READ_TCAM_REG_CTL(handle, val_p) \ argument
66 REG_PIO_READ64(handle, PFC_TCAM_CTRL, val_p)
77 #define READ_TCAM_REG_KEY0(handle, val_p) \ argument
78 REG_PIO_READ64(handle, PFC_TCAM_KEY0, val_p)
79 #define READ_TCAM_REG_KEY1(handle, val_p) \ argument
80 REG_PIO_READ64(handle, PFC_TCAM_KEY1, val_p)
81 #define READ_TCAM_REG_MASK0(handle, val_p) \ argument
82 REG_PIO_READ64(handle, PFC_TCAM_MASK0, val_p)
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H A Dhpi_txdma.h53 #define TXDMA_REG_READ64(handle, reg, channel, val_p) \ argument
55 (HXGE_TXDMA_OFFSET(reg, handle.is_vraddr, channel)), val_p)
/titanic_41/usr/src/uts/common/io/nxge/npi/
H A Dnpi_mac.h282 #define XMAC_REG_RD(handle, portn, reg, val_p)\ argument
283 NXGE_REG_RD64(handle, XMAC_REG_ADDR((portn), (reg)), (val_p))
288 #define BMAC_REG_RD(handle, portn, reg, val_p)\ argument
289 NXGE_REG_RD64(handle, BMAC_REG_ADDR((portn), (reg)), (val_p))
294 #define PCS_REG_RD(handle, portn, reg, val_p)\ argument
295 NXGE_REG_RD64(handle, PCS_REG_ADDR((portn), (reg)), (val_p))
300 #define XPCS_REG_RD(handle, portn, reg, val_p)\ argument
301 NXGE_REG_RD64(handle, XPCS_ADDR((portn), (reg)), (val_p))
306 #define MIF_REG_RD(handle, reg, val_p)\ argument
307 NXGE_REG_RD64(handle, MIF_ADDR((reg)), (val_p))
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H A Dnpi_txc.h67 #define TXC_FZC_REG_READ64(handle, reg, cn, val_p) \ argument
69 (NXGE_TXC_FZC_OFFSET(reg, cn)), val_p)
75 #define TXC_FZC_CNTL_REG_READ64(handle, reg, port, val_p) \ argument
77 (NXGE_TXC_FZC_CNTL_OFFSET(reg, port)), val_p)
H A Dnpi_espc.h38 #define EPC_WAIT_RW_COMP(handle, val_p, comp_bit) {\ argument
43 val_p); cnt--;\
H A Dnpi_txdma.h134 #define TX_LOG_REG_READ64(handle, reg, channel, val_p) \ argument
135 NXGE_REG_RD64(handle, NXGE_TXLOG_OFFSET(reg, channel), val_p)
/titanic_41/usr/src/uts/common/sys/nxge/
H A Dnxge_common_impl.h314 #define NXGE_REG_RD64(handle, offset, val_p) {\ argument
315 *(val_p) = NXGE_NPI_PIO_READ64(handle, offset);\
317 (uint64_t)(*(val_p)));\
324 #define NXGE_REG_RD64(handle, offset, val_p) {\ argument
325 *(val_p) = NXGE_NPI_PIO_READ64(handle, offset);\
326 rt_show_reg(0xbadbad, B_FALSE, (uint32_t)offset, (uint64_t)(*(val_p)));\
329 #define NXGE_REG_RD64(handle, offset, val_p) {\ argument
330 *(val_p) = NXGE_NPI_PIO_READ64(handle, offset);\
H A Dnxge_fflp_hw.h1097 #define REG_PIO_READ64(handle, offset, val_p) \ argument
1098 NXGE_REG_RD64((handle), (offset), (val_p))
1104 #define READ_TCAM_REG_CTL(handle, val_p) \ argument
1105 REG_PIO_READ64(handle, FFLP_TCAM_CTL_REG, val_p)
1125 #define READ_TCAM_REG_KEY0(handle, val_p) \ argument
1126 REG_PIO_READ64(handle, FFLP_TCAM_KEY_0_REG, val_p)
1127 #define READ_TCAM_REG_KEY1(handle, val_p) \ argument
1128 REG_PIO_READ64(handle, FFLP_TCAM_KEY_1_REG, val_p)
1129 #define READ_TCAM_REG_KEY2(handle, val_p) \ argument
1130 REG_PIO_READ64(handle, FFLP_TCAM_KEY_2_REG, val_p)
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/titanic_41/usr/src/uts/common/sys/
H A Dddi_obsolete.h132 int ddi_peekc(dev_info_t *dip, int8_t *addr, int8_t *val_p);
133 int ddi_peeks(dev_info_t *dip, int16_t *addr, int16_t *val_p);
134 int ddi_peekl(dev_info_t *dip, int32_t *addr, int32_t *val_p);
135 int ddi_peekd(dev_info_t *dip, int64_t *addr, int64_t *val_p);
H A Dsunddi.h580 int ddi_peek8(dev_info_t *dip, int8_t *addr, int8_t *val_p);
581 int ddi_peek16(dev_info_t *dip, int16_t *addr, int16_t *val_p);
582 int ddi_peek32(dev_info_t *dip, int32_t *addr, int32_t *val_p);
583 int ddi_peek64(dev_info_t *dip, int64_t *addr, int64_t *val_p);
/titanic_41/usr/src/uts/common/io/bnxe/577xx/drivers/common/include/
H A Dmm_ndismono.h198 #define mm_get_bar_size_imp(pdev, bar_num, val_p) \ argument
199 lm_get_bar_size_direct(pdev, bar_num, val_p)
H A Dmm_user_mode_debug.h212 #define mm_get_bar_size_imp(pdev, bar_num, val_p) \ argument
213 lm_get_bar_size_direct(pdev, bar_num, val_p)
H A Dmm_dos.h254 #define mm_get_bar_size_imp(pdev, bar_num, val_p) \ argument
255 lm_get_bar_size_direct(pdev, bar_num, val_p)
H A Dmm_solaris.h198 #define mm_get_bar_size_imp(pdev, bar_num, val_p) \ argument
199 lm_get_bar_size_direct(pdev, bar_num, val_p)
H A Dmm_uefi.h260 #define mm_get_bar_size_imp(pdev, bar_num, val_p) \ argument
261 lm_get_bar_size_direct(pdev, bar_num, val_p)
H A Dmm_vbd.h69 #define mm_get_bar_size_imp(pdev, bar_num, val_p) \ argument
70 lm_get_bar_size_direct(pdev, bar_num, val_p)
H A Dmm.h551 #define mm_get_bar_size(/* struct _lm_device_t* */pdev, /* u8_t */bar_num, /* u32_t* */val_p) \ argument
552 mm_get_bar_size_imp(pdev, bar_num, val_p)
/titanic_41/usr/src/uts/common/os/
H A Dsunddi.c409 ddi_peek8(dev_info_t *dip, int8_t *addr, int8_t *val_p) in ddi_peek8() argument
411 return (i_ddi_peekpoke(dip, DDI_CTLOPS_PEEK, sizeof (*val_p), addr, in ddi_peek8()
412 val_p)); in ddi_peek8()
416 ddi_peek16(dev_info_t *dip, int16_t *addr, int16_t *val_p) in ddi_peek16() argument
418 return (i_ddi_peekpoke(dip, DDI_CTLOPS_PEEK, sizeof (*val_p), addr, in ddi_peek16()
419 val_p)); in ddi_peek16()
423 ddi_peek32(dev_info_t *dip, int32_t *addr, int32_t *val_p) in ddi_peek32() argument
425 return (i_ddi_peekpoke(dip, DDI_CTLOPS_PEEK, sizeof (*val_p), addr, in ddi_peek32()
426 val_p)); in ddi_peek32()
430 ddi_peek64(dev_info_t *dip, int64_t *addr, int64_t *val_p) in ddi_peek64() argument
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/titanic_41/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/
H A Dlm_devinfo.c422 OUT u32_t * val_p) in lm_get_bar_size_direct() argument
454 *val_p = (0x40 << ((bar_size - 1)))*0x400; in lm_get_bar_size_direct()