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Searched refs:tdc (Results 1 – 20 of 20) sorted by relevance

/titanic_41/usr/src/uts/common/io/nxge/
H A Dnxge_txdma.c97 int i, tdc, count; in nxge_init_txdma_channels() local
110 for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) { in nxge_init_txdma_channels()
111 if ((1 << tdc) & map) { in nxge_init_txdma_channels()
113 group, VP_BOUND_TX, tdc))) in nxge_init_txdma_channels()
132 for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) { in nxge_init_txdma_channels()
133 if ((1 << tdc) & map) { in nxge_init_txdma_channels()
135 VP_BOUND_TX, tdc); in nxge_init_txdma_channels()
183 int tdc; in nxge_uninit_txdma_channels() local
193 for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) { in nxge_uninit_txdma_channels()
194 if ((1 << tdc) & set->owned.map) { in nxge_uninit_txdma_channels()
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H A Dnxge_send.c96 channel = nxgep->pt_config.hw_config.tdc.start + nrhp->index; in nxge_tx_ring_send()
204 "==> nxge_start: tx dma channel %d", tx_ring_p->tdc)); in nxge_start()
207 tx_ring_p->tdc, tx_ring_p->descs_pending)); in nxge_start()
338 tx_ring_p->tdc, in nxge_start()
354 tx_ring_p->tdc, mark_mode)); in nxge_start()
361 tx_ring_p->tdc)); in nxge_start()
364 tx_ring_p->tdc)); in nxge_start()
373 tx_ring_p->tdc)); in nxge_start()
471 tx_ring_p->tdc)); in nxge_start()
992 tx_ring_p->tdc, in nxge_start()
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H A Dnxge_virtual.c1926 p_cfgp->tdc.start = (func * NXGE_TDMA_PER_NIU_PORT); in nxge_use_default_dma_config_n2()
1929 p_cfgp->tdc.start = prop_val[0]; in nxge_use_default_dma_config_n2()
1932 "(#%d)", p_cfgp->tdc.start, prop_len)); in nxge_use_default_dma_config_n2()
1947 p_cfgp->tdc.count = ndmas; in nxge_use_default_dma_config_n2()
1948 p_cfgp->tdc.owned = p_cfgp->tdc.count; in nxge_use_default_dma_config_n2()
1952 p_cfgp, p_cfgp->tdc.count, p_cfgp->tdc.start)); in nxge_use_default_dma_config_n2()
1993 p_cfgp->max_grpids = p_cfgp->max_rdcs + p_cfgp->tdc.owned; in nxge_use_default_dma_config_n2()
2170 p_cfgp->tdc.start = *prop_val; in nxge_use_cfg_dma_config()
2207 p_cfgp->tdc.start = st_txdma; in nxge_use_cfg_dma_config()
2248 p_cfgp->tdc.count = tx_ndmas; in nxge_use_cfg_dma_config()
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H A Dnxge_ndd.c996 int tdc; in nxge_param_get_txdma_info() local
1020 for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) { in nxge_param_get_txdma_info()
1021 if ((1 << tdc) & set->owned.map) { in nxge_param_get_txdma_info()
1023 buf_len, "%d\n", tdc); in nxge_param_get_txdma_info()
2196 int tdc; in nxge_param_dump_tdc() local
2200 for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) { in nxge_param_dump_tdc()
2201 if ((1 << tdc) & set->owned.map) { in nxge_param_dump_tdc()
2202 (void) nxge_txdma_regs_dump(nxgep, tdc); in nxge_param_dump_tdc()
2308 int rdc, tdc, block; in nxge_param_dump_ptrs() local
2394 for (tdc = 0; tdc < p_cfgp->tdc.count; tdc++) { in nxge_param_dump_ptrs()
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H A Dnxge_intr.c272 limit = first + hardware->tdc.count; in nxge_intr_vec_find()
805 if (hardware->tdc.count == 0) { in nxge_hio_tdsv_add()
806 hardware->tdc.start = dc->channel; in nxge_hio_tdsv_add()
809 hardware->tdc.count++; in nxge_hio_tdsv_add()
810 hardware->tdc.owned++; in nxge_hio_tdsv_add()
H A Dnxge_hio_guest.c392 dc = &nhd->tdc[0]; in nxge_guest_dc_alloc()
479 hardware->tdc.start = first; in res_map_parse()
480 hardware->tdc.count = count; in res_map_parse()
481 hardware->tdc.owned = count; in res_map_parse()
H A Dnxge_main.c3065 dma_poolp->ndmas = p_cfgp->tdc.owned; in nxge_alloc_tx_mem_pool()
3072 dma_cntl_poolp->ndmas = p_cfgp->tdc.owned; in nxge_alloc_tx_mem_pool()
3087 nxgep->tx_rings->ndmas = p_cfgp->tdc.owned; in nxge_alloc_tx_mem_pool()
4467 cap_rings->mr_rnum = p_cfgp->tdc.count; in nxge_m_getcapab()
4484 p_cfgp->tdc.count)); in nxge_m_getcapab()
5543 channel = nxgep->pt_config.hw_config.tdc.start + rhp->index; in nxge_tx_ring_start()
5562 channel = nxgep->pt_config.hw_config.tdc.start + rhp->index; in nxge_tx_ring_stop()
5696 rtype, index, p_cfgp->tdc.count)); in nxge_fill_ring()
5698 ASSERT((index >= 0) && (index < p_cfgp->tdc.count)); in nxge_fill_ring()
5704 channel = nxgep->pt_config.hw_config.tdc.start + index; in nxge_fill_ring()
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H A Dnxge_kstats.c2171 int tdc = set[i]; in nxge_m_tx_stat() local
2174 val += statsp->tdc_stats[tdc].oerrors; in nxge_m_tx_stat()
2178 val += statsp->tdc_stats[tdc].obytes; in nxge_m_tx_stat()
2182 val += statsp->tdc_stats[tdc].opackets; in nxge_m_tx_stat()
2247 r_index = nxgep->pt_config.hw_config.tdc.start + rhp->index; in nxge_tx_ring_stat()
H A Dnxge_hio.c614 current = (type == VP_BOUND_TX) ? &nhd->tdc[0] : &nhd->rdc[0]; in nxge_grp_dc_find()
1634 offset = nxge->pt_config.hw_config.tdc.start; in nxge_hio_share_query()
2334 dc = type == MAC_RING_TYPE_TX ? &nhd->tdc[channel] : &nhd->rdc[channel]; in nxge_hio_dc_share()
/titanic_41/usr/src/uts/common/io/hxge/
H A Dhxge_txdma.c618 uint8_t tdc; in hxge_txdma_reclaim() local
642 tdc = tx_ring_p->tdc; in hxge_txdma_reclaim()
655 TXDMA_REG_READ64(handle, TDC_BYTE_CNT, tdc, &byte_cnt.value); in hxge_txdma_reclaim()
661 tdc, tx_rd_index, tail_index, tail_wrap, in hxge_txdma_reclaim()
668 TXDMA_REG_READ64(handle, TDC_TDR_HEAD, tdc, &tx_head.value); in hxge_txdma_reclaim()
680 TXDMA_REG_READ64(handle, TDC_TDR_QLEN, tdc, &qlen.value); in hxge_txdma_reclaim()
738 pkt_len, tdc, tdc_stats->opackets)); in hxge_txdma_reclaim()
954 channel = tx_desc_rings[i]->tdc; in hxge_txdma_hw_mode()
1085 channel = tx_rings->rings[index]->tdc; in hxge_fixup_txdma_rings()
1109 if (ring_p->tdc != channel) { in hxge_txdma_fix_channel()
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H A Dhxge_send.c150 "==> hxge_start: tx dma channel %d", tx_ring_p->tdc)); in hxge_start()
153 tx_ring_p->tdc, tx_ring_p->descs_pending)); in hxge_start()
201 tx_ring_p->tdc, mp->b_rptr, dump_len)); in hxge_start()
215 tx_ring_p->tdc, mark_mode)); in hxge_start()
219 "TX Descriptor ring is full: channel %d", tx_ring_p->tdc)); in hxge_start()
221 "TX Descriptor ring is full: channel %d", tx_ring_p->tdc)); in hxge_start()
782 tx_ring_p->tdc, tx_ring_p->wr_index, tx_ring_p->wr_index_wrap, in hxge_start()
792 TDC_TDR_KICK, (uint8_t)tx_ring_p->tdc, kick.value); in hxge_start()
H A Dhxge_txdma.h142 uint16_t tdc; member
182 uint16_t tdc; member
H A Dhxge_ndd.c1180 int rdc, tdc, block; in hxge_param_dump_ptrs() local
1258 for (tdc = 0; tdc < p_cfgp->max_tdcs; tdc++) { in hxge_param_dump_ptrs()
1260 " %d\t $%p\n", tdc, (void *)tx_rings[tdc]); in hxge_param_dump_ptrs()
H A Dhxge_virtual.c358 hxge_check_txdma_port_member(p_hxge_t hxgep, uint8_t tdc) in hxge_check_txdma_port_member() argument
370 if (tdc < p_cfgp->max_tdcs) in hxge_check_txdma_port_member()
H A Dhxge.h316 uint8_t tdc[HXGE_MAX_TDCS]; member
/titanic_41/usr/src/uts/common/io/nxge/npi/
H A Dnpi_txdma.c129 npi_txdma_dump_tdc_regs(npi_handle_t handle, uint8_t tdc) in npi_txdma_dump_tdc_regs() argument
135 ASSERT(TXDMA_CHANNEL_VALID(tdc)); in npi_txdma_dump_tdc_regs()
136 if (!TXDMA_CHANNEL_VALID(tdc)) { in npi_txdma_dump_tdc_regs()
140 tdc)); in npi_txdma_dump_tdc_regs()
142 return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(tdc)); in npi_txdma_dump_tdc_regs()
147 tdc)); in npi_txdma_dump_tdc_regs()
151 TXDMA_REG_READ64(handle, tdc_dmc_offset[i], tdc, &value); in npi_txdma_dump_tdc_regs()
153 tdc); in npi_txdma_dump_tdc_regs()
161 "\n TXDMA Register Dump for Channel %d done\n", tdc)); in npi_txdma_dump_tdc_regs()
208 npi_txdma_tdc_regs_zero(npi_handle_t handle, uint8_t tdc) in npi_txdma_tdc_regs_zero() argument
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H A Dnpi_txc.c143 npi_txc_dump_tdc_fzc_regs(npi_handle_t handle, uint8_t tdc) in npi_txc_dump_tdc_fzc_regs() argument
148 ASSERT(TXDMA_CHANNEL_VALID(tdc)); in npi_txc_dump_tdc_fzc_regs()
149 if (!TXDMA_CHANNEL_VALID(tdc)) { in npi_txc_dump_tdc_fzc_regs()
153 tdc)); in npi_txc_dump_tdc_fzc_regs()
154 return (NPI_FAILURE | NPI_TXC_CHANNEL_INVALID(tdc)); in npi_txc_dump_tdc_fzc_regs()
159 tdc)); in npi_txc_dump_tdc_fzc_regs()
163 offset = TXC_FZC_REG_CN_OFFSET(txc_fzc_dmc_offset[i], tdc); in npi_txc_dump_tdc_fzc_regs()
171 "\n TXC FZC Register Dump for Channel %d done\n", tdc)); in npi_txc_dump_tdc_fzc_regs()
/titanic_41/usr/src/uts/common/sys/nxge/
H A Dnxge_txdma.h158 uint16_t tdc; member
205 uint16_t tdc; member
H A Dnxge_hio.h312 nxge_hio_dc_t tdc[NXGE_MAX_TDCS]; member
H A Dnxge_common.h386 tdc_cfg_t tdc; member