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Searched refs:t4_write_reg (Results 1 – 6 of 6) sorted by relevance

/titanic_41/usr/src/uts/common/io/cxgbe/common/
H A Dt4_hw.c86 t4_write_reg(adapter, addr, v | val); in t4_set_reg_field()
108 t4_write_reg(adap, addr_reg, start_idx); in t4_read_indirect()
132 t4_write_reg(adap, addr_reg, start_idx++); in t4_write_indirect()
133 t4_write_reg(adap, data_reg, *vals++); in t4_write_indirect()
218 t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW)); in t4_wr_mbox_meat()
238 t4_write_reg(adap, ctl_reg, in t4_wr_mbox_meat()
249 t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE)); in t4_wr_mbox_meat()
277 t4_write_reg(adap, A_MC_BIST_CMD_ADDR, addr & ~0x3fU); in t4_mc_read()
278 t4_write_reg(adap, A_MC_BIST_CMD_LEN, 64); in t4_mc_read()
279 t4_write_reg(adap, A_MC_BIST_DATA_PATTERN, 0xc); in t4_mc_read()
[all …]
/titanic_41/usr/src/uts/common/io/cxgbe/t4nex/
H A Dadapter.c33 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) in t4_write_reg() function
H A Dt4_nexus.c401 t4_write_reg(sc, A_TP_SHIFT_CNT, V_SYNSHIFTMAX(6) | V_RXTSHIFTMAXR1(4) | in t4_devo_attach()
404 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12)); in t4_devo_attach()
800 t4_write_reg(sc, A_PL_RST, F_PIORSTMODE | F_PIORST); in t4_devo_quiesce()
1153 t4_write_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2), win); in upload_config_file()
1175 t4_write_reg(sc, MEMWIN2_BASE + off + i, *b++); in upload_config_file()
1386 t4_write_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 0), in setup_memwin()
1390 t4_write_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 1), in setup_memwin()
1394 t4_write_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2), in setup_memwin()
2103 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), in enable_port_queues()
2114 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), in enable_port_queues()
H A Dt4_sge.c277 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0, rx_buf_size); in t4_sge_init()
279 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, in t4_sge_init()
285 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, in t4_sge_init()
288 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, in t4_sge_init()
291 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, in t4_sge_init()
664 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0); in t4_intr_err()
752 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), in service_iq()
788 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_CIDXINC(ndescs) | in service_iq()
1222 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_SEINTARM(iq->intr_params) | in alloc_iq_fl()
2823 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), in ring_tx_db()
[all …]
H A Dt4_ioctl.c132 t4_write_reg(sc, r.reg, r.value); in reg_rw()
546 t4_write_reg(sc, in read_card_mem()
H A Dadapter.h569 void t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val);