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Searched refs:t1_tpi_write (Results 1 – 12 of 12) sorted by relevance

/titanic_41/usr/src/uts/common/io/chxge/com/
H A Dpm3393.c103 (void) t1_tpi_write(cmac->adapter, OFFSET(reg), data32); in pmwrite()
163 (void) t1_tpi_write(cmac->adapter, A_ELMER0_INT_ENABLE, elmer); in pm3393_interrupt_enable()
202 (void) t1_tpi_write(cmac->adapter, A_ELMER0_INT_ENABLE, elmer); in pm3393_interrupt_disable()
245 (void) t1_tpi_write(cmac->adapter, A_ELMER0_INT_CAUSE, elmer); in pm3393_interrupt_clear()
744 (void) t1_tpi_write(adapter, OFFSET(0x0001), 0x00008000); in pm3393_mac_create()
745 (void) t1_tpi_write(adapter, OFFSET(0x0001), 0x00000000); in pm3393_mac_create()
746 (void) t1_tpi_write(adapter, OFFSET(0x2308), 0x00009800); in pm3393_mac_create()
747 (void) t1_tpi_write(adapter, OFFSET(0x2305), 0x00001001); /* PL4IO Enable */ in pm3393_mac_create()
748 (void) t1_tpi_write(adapter, OFFSET(0x2320), 0x00008800); in pm3393_mac_create()
749 (void) t1_tpi_write(adapter, OFFSET(0x2321), 0x00008800); in pm3393_mac_create()
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H A Dixf1010.c171 (void) t1_tpi_write(mac->adapter, REG_PORT_ENABLE, val); in disable_port()
238 (void) t1_tpi_write(mac->adapter, MACREG(mac, REG_MACADDR_LOW), addr_lo); in mac_set_address()
239 (void) t1_tpi_write(mac->adapter, MACREG(mac, REG_MACADDR_HIGH), addr_hi); in mac_set_address()
281 (void) t1_tpi_write(adapter, MACREG(mac, REG_RX_FILTER), new_mode); in mac_set_rx_mode()
284 (void) t1_tpi_write(adapter, MACREG(mac, REG_MC_ADDR_LOW), 0); in mac_set_rx_mode()
285 (void) t1_tpi_write(adapter, MACREG(mac, REG_MC_ADDR_HIGH), 0); in mac_set_rx_mode()
292 (void) t1_tpi_write(adapter, MACREG(mac, REG_MC_ADDR_LOW), addr_lo); in mac_set_rx_mode()
293 (void) t1_tpi_write(adapter, MACREG(mac, REG_MC_ADDR_HIGH), addr_hi); in mac_set_rx_mode()
305 (void) t1_tpi_write(mac->adapter, MACREG(mac, REG_MAX_FRAME_SIZE), in mac_set_mtu()
322 (void) t1_tpi_write(mac->adapter, MACREG(mac, REG_RGMII_SPEED), val); in mac_set_speed_duplex_fc()
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H A Dmy3126.c99 (void) t1_tpi_write(adapter, OFFSET(SUNI1x10GEXP_REG_MSTAT_CONTROL), in my3126_interrupt_handler()
110 (void) t1_tpi_write(adapter, A_ELMER0_GPO, val); in my3126_interrupt_handler()
114 (void) t1_tpi_write(adapter, A_ELMER0_GPO, val); in my3126_interrupt_handler()
154 (void) t1_tpi_write(adapter, A_ELMER0_GPO, val); in my3126_get_link_status()
224 (void) t1_tpi_write(adapter, A_ELMER0_GPO, val); in my3126_phy_reset()
227 (void) t1_tpi_write(adapter, A_ELMER0_GPO, val | 4); in my3126_phy_reset()
233 (void) t1_tpi_write(adapter, A_ELMER0_GPO, val); in my3126_phy_reset()
H A Dmv88x201x.c86 (void) t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer); in mv88x201x_interrupt_enable()
102 (void) t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer); in mv88x201x_interrupt_disable()
139 (void) t1_tpi_write(cphy->adapter, A_ELMER0_INT_CAUSE, elmer); in mv88x201x_interrupt_clear()
249 (void) t1_tpi_write(adapter, A_ELMER0_GPO, val); in mv88x201x_phy_reset()
252 (void) t1_tpi_write(adapter, A_ELMER0_GPO, val | 4); in mv88x201x_phy_reset()
258 (void) t1_tpi_write(adapter, A_ELMER0_GPO, val); in mv88x201x_phy_reset()
H A Dxpak.c131 (void) t1_tpi_write(adapter, A_ELMER0_GPO, val); in xpak_phy_reset()
138 (void) t1_tpi_write(adapter, A_ELMER0_GPO, val | 4); in xpak_phy_reset()
146 (void) t1_tpi_write(adapter, A_ELMER0_GPO, val); in xpak_phy_reset()
H A Dvsc7321.c86 (void) t1_tpi_write(adapter, (addr << 2) + 4, data & 0xFFFF); in vsc_write()
87 (void) t1_tpi_write(adapter, addr << 2, (data >> 16) & 0xFFFF); in vsc_write()
97 (void) t1_tpi_write(adapter, A_ELMER0_GPO, val); in vsc7321_full_reset()
106 (void) t1_tpi_write(adapter, A_ELMER0_GPO, val); in vsc7321_full_reset()
H A Dmv88e1xxx.c106 (void) t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer); in mv88e1xxx_interrupt_enable()
125 (void) t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer); in mv88e1xxx_interrupt_disable()
144 (void) t1_tpi_write(cphy->adapter, A_ELMER0_INT_CAUSE, elmer); in mv88e1xxx_interrupt_clear()
H A Dch_subr.c103 t1_tpi_write(adapter_t *adapter, u32 addr, u32 value) in t1_tpi_write() function
352 (void) t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_CFG, val); in mi1_mdio_init()
968 (void) t1_tpi_write(adapter, A_ELMER0_INT_CAUSE, cause); in elmer0_ext_intr_handler()
1161 (void) t1_tpi_write(adapter, A_ELMER0_GPO, gpo); in power_sequence_xpak()
1200 (void) t1_tpi_write(adapter, A_ELMER0_GPO, 0x800); in board_init()
1204 (void) t1_tpi_write(adapter, A_ELMER0_GPO, 0x1800); in board_init()
1216 (void) t1_tpi_write(adapter, A_ELMER0_GPO, 0x804); in board_init()
1221 (void) t1_tpi_write(adapter, A_ELMER0_GPO, 0x1804); in board_init()
H A Dvsc7326.c86 (void) t1_tpi_write(adapter, (addr << 2) + 4, data & 0xFFFF); in vsc_write()
87 (void) t1_tpi_write(adapter, addr << 2, (data >> 16) & 0xFFFF); in vsc_write()
102 (void) t1_tpi_write(adapter, A_ELMER0_GPO, val); in vsc7326_full_reset()
106 (void) t1_tpi_write(adapter, A_ELMER0_GPO, val); in vsc7326_full_reset()
H A Dcommon.h240 int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value);
/titanic_41/usr/src/uts/common/io/chxge/
H A Dglue.c335 (void) t1_tpi_write(chp, te->addr, te->val); in pe_ioctl()
H A Dsge.c1034 (void) t1_tpi_write(adapter, in t1_sge_check_pause()
1046 (void) t1_tpi_write(adapter, in t1_sge_check_pause()