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Searched refs:t1_read_reg_4 (Results 1 – 14 of 14) sorted by relevance

/titanic_41/usr/src/uts/common/io/chxge/com/
H A Dmc4.c51 u32 mc4_cfg = t1_read_reg_4(adapter, A_MC4_CFG); in mc4_calc_size()
69 val = t1_read_reg_4(adapter, addr); /* flush */ in wrreg_wait()
71 if (!(t1_read_reg_4(adapter, addr) & F_BUSY)) in wrreg_wait()
91 val = t1_read_reg_4(adapter, A_MC4_CFG); in t1_mc4_init()
93 val = t1_read_reg_4(adapter, A_MC4_CFG); /* flush */ in t1_mc4_init()
102 val = t1_read_reg_4(adapter, A_MC4_STROBE); in t1_mc4_init()
115 val = t1_read_reg_4(adapter, A_MC4_STROBE); in t1_mc4_init()
123 val = t1_read_reg_4(adapter, A_MC4_STROBE); in t1_mc4_init()
145 val = t1_read_reg_4(adapter, A_MC4_REFRESH); in t1_mc4_init()
161 (void) t1_read_reg_4(adapter, A_MC4_REFRESH); /* flush */ in t1_mc4_init()
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H A Dmc3.c48 u32 en = t1_read_reg_4(mc3->adapter, A_PL_ENABLE); in t1_mc3_intr_enable()
65 u32 pl_intr = t1_read_reg_4(mc3->adapter, A_PL_ENABLE); in t1_mc3_intr_disable()
90 old_en = t1_read_reg_4(mc3->adapter, A_MC3_INT_ENABLE); in t1_mc3_intr_clear()
119 cause = t1_read_reg_4(adapter, cause_reg); in t1_mc3_intr_handler()
126 G_MC3_CE_ADDR(t1_read_reg_4(adapter, A_MC3_CE_ADDR)), in t1_mc3_intr_handler()
127 t1_read_reg_4(adapter, A_MC3_CE_DATA0), in t1_mc3_intr_handler()
128 t1_read_reg_4(adapter, A_MC3_CE_DATA1), in t1_mc3_intr_handler()
129 t1_read_reg_4(adapter, A_MC3_CE_DATA2), in t1_mc3_intr_handler()
130 t1_read_reg_4(adapter, A_MC3_CE_DATA3), in t1_mc3_intr_handler()
131 t1_read_reg_4(adapter, A_MC3_CE_DATA4)); in t1_mc3_intr_handler()
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H A Dch_mac.c92 mac_intr = t1_read_reg_4(mac->adapter, A_PL_ENABLE); in mac_intr_enable()
96 mac_intr = t1_read_reg_4(mac->adapter, in mac_intr_enable()
118 mac_intr = t1_read_reg_4(mac->adapter, A_PL_ENABLE); in mac_intr_disable()
122 mac_intr = t1_read_reg_4(mac->adapter, in mac_intr_disable()
147 mac_intr = t1_read_reg_4(mac->adapter, in mac_intr_clear()
161 data32_lo = t1_read_reg_4(mac->adapter, in mac_get_address()
163 data32_hi = t1_read_reg_4(mac->adapter, in mac_get_address()
181 data32 = t1_read_reg_4(mac->adapter, MAC_REG_CSR(idx)); in mac_reset()
186 data32 = t1_read_reg_4(mac->adapter, in mac_reset()
206 val = t1_read_reg_4(mac->adapter, in mac_set_rx_mode()
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H A Despi.c85 status = t1_read_reg_4(adapter, A_ESPI_GOSTAT);
101 if (!(t1_read_reg_4(adapter, A_ESPI_RX_RESET) & F_RX_CLK_STATUS)) { in tricn_init()
129 u32 enable, pl_intr = t1_read_reg_4(espi->adapter, A_PL_ENABLE); in t1_espi_intr_enable()
145 (void) t1_read_reg_4(espi->adapter, A_ESPI_DIP2_ERR_COUNT); in t1_espi_intr_clear()
152 u32 pl_intr = t1_read_reg_4(espi->adapter, A_PL_ENABLE); in t1_espi_intr_disable()
160 u32 status = t1_read_reg_4(espi->adapter, A_ESPI_INTR_STATUS); in t1_espi_intr_handler()
174 (void) t1_read_reg_4(espi->adapter, A_ESPI_DIP2_ERR_COUNT); in t1_espi_intr_handler()
299 espi->misc_ctrl = t1_read_reg_4(adapter, A_ESPI_MISC_CONTROL); in t1_espi_init()
357 sel = t1_read_reg_4(adapter, A_ESPI_SCH_TOKEN3); in t1_espi_get_mon()
362 sel = t1_read_reg_4(adapter, A_ESPI_SCH_TOKEN3); in t1_espi_get_mon()
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H A Dtp.c93 u32 tr = t1_read_reg_4(adap, A_TP_TIMER_RESOLUTION); in tp_delayed_ack_ticks()
100 u32 tr = t1_read_reg_4(adap, A_TP_TIMER_RESOLUTION); in t1_tp_ticks_per_sec()
124 tp_scnt = t1_read_reg_4(adapter, A_TP_SHIFT_CNT); in tp_set_tcp_time_params()
141 val = t1_read_reg_4(tp->adapter, A_TP_PARA_REG3); in t1_tp_set_coalescing_size()
169 *data++ = t1_read_reg_4(adap, A_TP_MIB_DATA); in t1_tp_get_mib_statistics()
268 val = t1_read_reg_4(ap, A_TP_PC_CONFIG); in tp_init()
319 u32 tp_intr = t1_read_reg_4(tp->adapter, A_PL_ENABLE); in t1_tp_intr_enable()
340 u32 tp_intr = t1_read_reg_4(tp->adapter, A_PL_ENABLE); in t1_tp_intr_disable()
381 cause = t1_read_reg_4(tp->adapter, A_TP_INT_CAUSE); in t1_tp_intr_handler()
388 u32 val = t1_read_reg_4(tp->adapter, A_TP_GLOBAL_CONFIG); in set_csum_offload()
H A Dmc5.c149 return t1_read_reg_4(mc5->adapter, A_MC5_ROUTING_TABLE_INDEX); in t1_mc5_get_tcam_rtbl_base()
169 return t1_read_reg_4(mc5->adapter, A_MC5_SERVER_INDEX); in t1_mc5_get_tcam_server_base()
196 *v1 = t1_read_reg_4(adapter, A_MC5_DBGI_RSP_DATA0); in dbgi_rd_rsp3()
197 *v2 = t1_read_reg_4(adapter, A_MC5_DBGI_RSP_DATA1); in dbgi_rd_rsp3()
198 *v3 = t1_read_reg_4(adapter, A_MC5_DBGI_RSP_DATA2); in dbgi_rd_rsp3()
412 cfg = t1_read_reg_4(adap, A_MC5_CONFIG) & ~F_MODE; in t1_mc5_init()
520 u32 pl_intr = t1_read_reg_4(mc5->adapter, A_PL_ENABLE); in t1_mc5_intr_enable()
538 u32 pl_intr = t1_read_reg_4(mc5->adapter, A_PL_ENABLE); in t1_mc5_intr_disable()
565 u32 cause = t1_read_reg_4(adap, A_MC5_INT_CAUSE); in t1_mc5_intr_handler()
648 cfg = t1_read_reg_4(adapter, A_MC5_CONFIG); in t1_mc5_create()
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H A Dulp.c47 u32 pl_intr = t1_read_reg_4(ulp->adapter, A_PL_ENABLE); in t1_ulp_intr_enable()
66 u32 pl_intr = t1_read_reg_4(ulp->adapter, A_PL_ENABLE); in t1_ulp_intr_disable()
76 u32 cause = t1_read_reg_4(ulp->adapter, A_ULP_INT_CAUSE); in t1_ulp_intr_handler()
H A Dch_subr.c67 u32 val = t1_read_reg_4(adapter, reg) & mask; in t1_wait_op_done()
131 *valp = t1_read_reg_4(adapter, A_TPI_RD_DATA); in __t1_tpi_read()
207 u32 cause = t1_read_reg_4(adapter, FPGA_GMAC_ADDR_INTERRUPT_CAUSE); in fpga_phy_intr_handler()
226 u32 cause = t1_read_reg_4(adapter, A_PL_CAUSE); in fpga_slow_intr()
240 u32 tp_cause = t1_read_reg_4(adapter, in fpga_slow_intr()
283 if (t1_read_reg_4(adapter, A_MI0_CSR) & F_MI0_BUSY) { in fpga_mdio_read()
290 *val = t1_read_reg_4(adapter, A_MI0_DATA_EXT); in fpga_mdio_read()
302 if (t1_read_reg_4(adapter, A_MI0_CSR) & F_MI0_BUSY) { in fpga_mdio_write()
1012 u32 pl_intr = t1_read_reg_4(adapter, A_PL_ENABLE); in t1_interrupts_enable()
1090 u32 pl_intr = t1_read_reg_4(adapter, A_PL_CAUSE); in t1_interrupts_clear()
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H A Dcspi.c50 *status = t1_read_reg_4(cspi->adapter, A_CSPI_INTR_STATUS); in t1_cspi_intr_status_read()
H A Dpm3393.c167 pl_intr = t1_read_reg_4(cmac->adapter, A_PL_ENABLE); in pm3393_interrupt_enable()
249 pl_intr = t1_read_reg_4(cmac->adapter, A_PL_CAUSE); in pm3393_interrupt_clear()
/titanic_41/usr/src/uts/common/io/chxge/
H A Dglue.c90 t1_read_reg_4(ch_t *obj, uint32_t reg_val) in t1_read_reg_4() function
222 pe->pe_reg_val = reg = t1_read_reg_4(chp, pe->addr); in pe_ioctl()
240 reg = t1_read_reg_4(chp, pe->addr); in pe_ioctl()
H A Dch.h285 uint32_t t1_read_reg_4(ch_t *obj, uint32_t reg_val);
H A Dsge.c289 status = t1_read_reg_4(sge->obj, A_SG_INT_CAUSE); in sge_stop()
507 u32 val = t1_read_reg_4(sge->obj, A_PL_ENABLE); in t1_sge_intr_disable()
524 u32 val = t1_read_reg_4(sge->obj, A_PL_ENABLE); in t1_sge_intr_enable()
551 u32 cause = t1_read_reg_4(obj, A_SG_INT_CAUSE); in t1_sge_intr_error_handler()
1138 u32 irq_reg = t1_read_reg_4(sge->obj, A_SG_INT_ENABLE); in freelQs_empty()
H A Dpe.c1520 enable = t1_read_reg_4(adapter, A_PL_ENABLE); in ext_intr_task()
1531 u32 enable = t1_read_reg_4(adapter, A_PL_ENABLE); in t1_os_elmer0_ext_intr()