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Searched refs:shmem_base (Results 1 – 7 of 7) sorted by relevance

/titanic_41/usr/src/uts/common/io/bnxe/577xx/common/
H A Dbnxe_clc.c395 link_status = REG_RD(cb, params->shmem_base + in elink_check_lfa()
2353 REG_WR(cb, params->shmem_base + in elink_update_mng()
3171 eee_mode = ((REG_RD(cb, params->shmem_base + in elink_eee_calc_timer()
3347 board_cfg = REG_RD(cb, params->shmem_base + in elink_bsc_module_sel()
3355 sfp_ctrl = REG_RD(cb, params->shmem_base + in elink_bsc_module_sel()
4112 if (REG_RD(cb, params->shmem_base + in elink_warpcore_enable_AN_KR()
4152 wc_lane_config = REG_RD(cb, params->shmem_base + in elink_warpcore_enable_AN_KR()
4303 cfg_tap_val = REG_RD(cb, params->shmem_base + in elink_warpcore_set_10G_XFI()
4618 u32 shmem_base, u8 port, in elink_get_mod_abs_int_cfg() argument
4625 cfg_pin = (REG_RD(cb, shmem_base + in elink_get_mod_abs_int_cfg()
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/titanic_41/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A Dclc.h388 u32 shmem_base; member
594 u8 elink_fan_failure_det_req(struct elink_dev *cb, u32 shmem_base,
691 u32 chip_id, u32 shmem_base, u32 shmem2_base,
709 u32 shmem_base,
/titanic_41/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/
H A Dlm_phy.c1833 u32_t shmem_base[MAX_PATH_NUM], shmem_base2[MAX_PATH_NUM]; in lm_update_external_phy_fw_prepare() local
1834 shmem_base[0] = pdev->hw_info.shmem_base; in lm_update_external_phy_fw_prepare()
1839 LM_SHMEM2_READ(pdev, OFFSETOF(shmem2_region_t,other_shmem_base_addr), &shmem_base[1]); in lm_update_external_phy_fw_prepare()
1843 elink_common_init_phy(pdev, shmem_base, shmem_base2, CHIP_ID(pdev), 0); in lm_update_external_phy_fw_prepare()
1844 elink_pre_init_phy(pdev, shmem_base[0], shmem_base2[0], CHIP_ID(pdev), 0); in lm_update_external_phy_fw_prepare()
H A Dlm_devinfo.c1772 pdev->hw_info.shmem_base = 0; in lm_shmem_set_default()
1994 …offset = pdev->hw_info.shmem_base + OFFSETOF(shmem_region_t, func_mb) + E1H_FUNC_MAX * sizeof(stru… in lm_get_shmem_mf_cfg_base()
2619 pdev->hw_info.shmem_base = val; in lm_get_shmem_info()
2625 pdev->hw_info.shmem_base, pdev->hw_info.shmem_base2, pdev->hw_info.mf_cfg_base); in lm_get_shmem_info()
2696 pdev->params.link.shmem_base = NO_MCP_WA_CLC_SHMEM; in init_link_params()
2701 pdev->params.link.shmem_base = pdev->hw_info.shmem_base; in init_link_params()
H A Dlm_hw_init_reset.c4194 u32_t shmem_base[MAX_PATH_NUM] = {0}; in init_common_part() local
4284 shmem_base[0] = pdev->hw_info.shmem_base; in init_common_part()
4289 LM_SHMEM2_READ(pdev, OFFSETOF(shmem2_region_t,other_shmem_base_addr), &shmem_base[1]); in init_common_part()
4296 rc = elink_common_init_phy(pdev, shmem_base, shmem_base2, CHIP_ID(pdev), 0); in init_common_part()
4299 rc = elink_pre_init_phy(pdev, shmem_base[0], shmem_base2[0], CHIP_ID(pdev), port); in init_common_part()
4389 …elink_init_mod_abs_int(pdev, &pdev->vars.link, CHIP_ID(pdev), pdev->hw_info.shmem_base, pdev->hw_i… in init_port_part()
H A Dlm_hw_access.c362 …is_required |= elink_fan_failure_det_req(pdev, pdev->hw_info.shmem_base, pdev->hw_info.shmem_base2… in lm_setup_fan_failure_detection()
/titanic_41/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/include/
H A Dlm5710.h1019 #define SHMEM_BASE(pdev) (pdev->hw_info.shmem_base)
1630 u32_t shmem_base; /* Firmware share memory base addr. */ member
4217 #define LM_SHMEM_READ(_pdev,_offset,_ret) LM_SHMEM_READ_IMP(_pdev,_offset,_ret, shmem_base );
4224 #define LM_SHMEM_WRITE(_pdev,_offset,_val) LM_SHMEM_WRITE_IMP(_pdev,_offset,_val,shmem_base);