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Searched refs:serd (Results 1 – 21 of 21) sorted by relevance

/titanic_41/usr/src/cmd/fm/eversholt/files/i386/i86pc/
H A Dintel.esc56 engine serd.cpu.intel.simple@chip/core/strand, N=3, T=72h;
58 engine=serd.cpu.intel.simple@chip/core/strand;
138 engine serd.cpu.intel.fltleaf@chip/core/strand, N=n, T=t; \
140 engine=serd.cpu.intel.fltleaf@chip/core/strand; \
150 engine serd.cpu.intel.fltleaf@chip/core/strand, N=n, T=t; \
152 engine=serd.cpu.intel.fltleaf@chip/core/strand; \
273 engine serd.memory.intel.page_ce@MBDIMM/rank, N=PAGE_CE_COUNT, T=PAGE_CE_TIME;
275 count=stat.ce_pgflt@MBDIMM, engine=serd.memory.intel.page_ce@MBDIMM/rank;
282 engine serd.memory.intel.dimm_ce@MBDIMM/rank, N=DIMM_CE_COUNT, T=DIMM_CE_TIME;
284 engine=serd.memory.intel.dimm_ce@MBDIMM/rank;
[all …]
H A Dgcpu.esc63 engine serd.cpu.generic-x86.simple@chip/core/strand, N=SMPL_N, T=72h;
65 engine=serd.cpu.generic-x86.simple@chip/core/strand;
146 * error by incrementing the serd engine by n + 1.
150 engine serd.cpu.generic-x86.fltleaf@chip/core/strand, N=n, T=t; \
152 engine=serd.cpu.generic-x86.fltleaf@chip/core/strand; \
161 engine serd.cpu.generic-x86.fltleaf@chip/core/strand, N=n, T=t; \
163 response=0, engine=serd.cpu.generic-x86.fltleaf@chip/core/strand;\
H A Damd64.esc111 * single-bit errors, but via separate serd engines to allow distinct
147 engine serd.memory.page_sb@chip/memory-controller/dimm/rank,
149 engine serd.memory.page_ck@chip/memory-controller/dimm/rank,
151 engine serd.memory.dimm_sb@chip/memory-controller/dimm/rank,
153 engine serd.memory.dimm_ck@chip/memory-controller/dimm/rank,
157 engine=serd.memory.page_sb@chip/memory-controller/dimm/rank;
160 engine=serd.memory.page_ck@chip/memory-controller/dimm/rank;
162 engine=serd.memory.dimm_sb@chip/memory-controller/dimm/rank;
164 engine=serd.memory.dimm_ck@chip/memory-controller/dimm/rank;
389 engine serd.cpu.amd.l2d_sb@chip/core/strand,
[all …]
H A Dgcpu_amd.esc132 engine serd.memory.generic-x86.page_ce@CSPATH, N=PAGE_SB_COUNT, T=PAGE_SB_TIME;
136 engine=serd.memory.generic-x86.page_ce@CSPATH;
137 engine serd.memory.generic-x86.dimm_ce@CSPATH, N=PAGE_SB_COUNT, T=PAGE_SB_TIME;
139 engine=serd.memory.generic-x86.dimm_ce@CSPATH;
/titanic_41/usr/src/cmd/fm/eversholt/files/sparc/sun4v/
H A Dgcpu.esc63 * serd.cpu.generic-sparc.<resource><suffix>
64 * Ex: serd.cpu.generic-sparc.chipitlb
230 * The serd name & the N & T values are set at the running time.
232 engine serd.cpu.generic-sparc.core@core, N=8, T=1week;
233 engine serd.cpu.generic-sparc.strand@strand, N=8, T=1week;
240 engine=serd.cpu.generic-sparc.fltleaf@level; \
274 engine serd.cpu.generic-sparc.chip-nr@chip, N=8, T=1week;
275 engine serd.cpu.generic-sparc.core-nr@core, N=8, T=1week;
276 engine serd.cpu.generic-sparc.strand-nr@strand, N=8, T=1week;
283 engine=serd.cpu.generic-sparc.fltleaf@level; \
[all …]
H A Dgmem.esc107 engine serd.memory.generic-sparc.membuf-crc@CHIP, N=120, T=30min;
108 engine serd.memory.generic-sparc.membuf-crc@MEM_BUFF, N=120, T=30min;
109 engine serd.memory.generic-sparc.membuf-crc@MEM_CTRL, N=120, T=30min;
113 engine=serd.memory.generic-sparc.membuf-crc@CHIP;
115 engine=serd.memory.generic-sparc.membuf-crc@MEM_BUFF;
117 engine=serd.memory.generic-sparc.membuf-crc@MEM_CTRL;
154 engine serd.memory.generic-sparc.membuf-crc@CHIP/MEM_BUFF, N=120, T=30min;
156 engine=serd.memory.generic-sparc.membuf-crc@CHIP/MEM_BUFF;
223 engine serd.cpu.generic-sparc.membuf-crc@MEM_CTRL/MEM_BUFF, N=120, T=30min;
225 engine=serd.cpu.generic-sparc.membuf-crc@MEM_CTRL/MEM_BUFF;
H A Dzambezi.esc335 * automatically. Instead, we explicitly declare 4 sets of serd engine
356 engine serd.asic.ultraSPARC-T2plus.interconnect.lfu.chip0@interconnect,
361 engine=serd.asic.ultraSPARC-T2plus.interconnect.lfu.chip0@interconnect;
364 engine=serd.asic.ultraSPARC-T2plus.interconnect.lfu.chip0@interconnect;
381 engine serd.asic.ultraSPARC-T2plus.interconnect.lfu.chip1@interconnect,
386 engine=serd.asic.ultraSPARC-T2plus.interconnect.lfu.chip1@interconnect;
389 engine=serd.asic.ultraSPARC-T2plus.interconnect.lfu.chip1@interconnect;
406 engine serd.asic.ultraSPARC-T2plus.interconnect.lfu.chip2@interconnect,
411 engine=serd.asic.ultraSPARC-T2plus.interconnect.lfu.chip2@interconnect;
414 engine=serd.asic.ultraSPARC-T2plus.interconnect.lfu.chip2@interconnect;
[all …]
H A Dn2piu.esc258 engine serd.io.device.nonfatal@niu/niufn,
263 engine=serd.io.device.nonfatal@niu/niufn;
/titanic_41/usr/src/cmd/fm/eversholt/files/sparc/SUNW,Sun-Fire-15000/
H A DSUNW,Sun-Fire-15000.esc61 engine serd.io.cpu.ecc@cpu,
66 engine=serd.io.cpu.ecc@cpu;
/titanic_41/usr/src/cmd/fm/eversholt/common/
H A Dtree.c1062 struct node *serd; in update_serd_refstmt() local
1066 serd = tree_s2np_lut_lookup(((struct node *)rhs)->u.stmt.lutp, in update_serd_refstmt()
1068 if (serd == NULL) in update_serd_refstmt()
1071 ASSERT(serd->t == T_EVENT); in update_serd_refstmt()
1072 if (arg != NULL && tree_eventcmp(serd, (struct node *)arg) != 0) in update_serd_refstmt()
1075 serd = tree_event2np_lut_lookup(SERDs, serd); in update_serd_refstmt()
1076 if (serd != NULL) in update_serd_refstmt()
1077 serd->u.stmt.flags |= STMT_REF; in update_serd_refstmt()
H A Dliterals.h71 L_DECL(serd);
/titanic_41/usr/src/cmd/fm/eversholt/files/sparc/sun4u/
H A Dpsycho.esc64 engine serd.io.psycho.ecc@hostbridge,
69 engine=serd.io.psycho.ecc@hostbridge;
243 engine serd.io.psy.nodiag@hostbridge,
248 engine=serd.io.psy.nodiag@hostbridge;
H A Doberon.esc145 engine serd.io.oberon.nodiag@hostbridge,
150 engine=serd.io.oberon.nodiag@hostbridge;
H A Dschizo.esc123 engine serd.io.schizo.ecc@hostbridge,
128 engine=serd.io.schizo.ecc@hostbridge;
425 engine serd.io.sch.nodiag@hostbridge,
430 engine=serd.io.sch.nodiag@hostbridge;
H A Dxmits.esc147 engine serd.io.xmits.ecc@hostbridge,
152 engine=serd.io.xmits.ecc@hostbridge;
433 engine serd.io.xmits.nodiag@hostbridge,
438 engine=serd.io.xmits.nodiag@hostbridge;
H A Dtomatillo.esc396 engine serd.io.tom.nodiag@hostbridge,
401 engine=serd.io.tom.nodiag@hostbridge;
/titanic_41/usr/src/cmd/fm/eversholt/files/common/
H A Ddisk.esc49 engine serd.io.scsi.cmd.disk.dev.rqs.merr@P, N=1, T=24h;
56 engine=serd.io.scsi.cmd.disk.dev.rqs.merr@P;
116 * the serd engine would only trigger if the fault recurred on the same LBA
H A Dpciexrc.esc103 engine serd.io.pciex.rc.generic-ce@hostbridge, N=RC_N, T=RC_T;
105 engine=serd.io.pciex.rc.generic-ce@hostbridge;
H A Dpciex.esc57 * we have tighter serd parameters for these. These are most likely errors in
120 engine serd.io.pciex.flt-nf@PCIEXFN, N=NONFATAL_DPE_COUNT, T=NONFATAL_DPE_TIME;
122 engine=serd.io.pciex.flt-nf@PCIEXFN;
124 engine serd.io.device.nonfatal@PCIEXFN, N=CORRLINK_COUNT, T=CORRLINK_TIME;
126 engine=serd.io.device.nonfatal@PCIEXFN;
127 engine serd.io.device.nonfatal@PCIEXFN/PCIEXFN,
130 engine=serd.io.device.nonfatal@PCIEXFN/PCIEXFN;
131 engine serd.io.device.nonfatal@pciexrc/PCIEXFN,
134 engine=serd.io.device.nonfatal@pciexrc/PCIEXFN;
140 engine serd.io.pciex.flt-nf@pciexrc, N=NONFATAL_DPE_COUNT, T=NONFATAL_DPE_TIME;
[all …]
H A Dpci.esc38 * serd parameters for these. These are most likely errors in buffers/caches
53 engine serd.io.device.nonfatal@PCIFN,
56 engine serd.io.pci.nf-dpe@PCIFN,
59 engine serd.io.pci.nf-dpe-bus@pcibus,
86 engine=serd.io.device.nonfatal@PCIFN, FITrate=PCI_DEV_FIT;
89 engine=serd.io.pci.nf-dpe@PCIFN, FITrate=PCI_DEV_FIT;
515 engine=serd.io.pci.nf-dpe-bus@pcibus, FITrate=PCI_BUS_FIT;
1090 * Handling of leaf driver detected internal errors. Use serd engine if
1150 * - ignore ecc.ce ereports for now (could do serd on these)
/titanic_41/usr/src/cmd/fm/eversholt/files/sparc/sun4/
H A Dfire.esc547 engine serd.io.fire.link-events@hostbridge/pciexrc,
552 engine=serd.io.fire.link-events@hostbridge/pciexrc ;
639 engine=serd.io.fire.fabric@pciexbus/pciexdev/pciexfn;
641 engine serd.io.fire.fabric@pciexbus/pciexdev/pciexfn,