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Searched refs:regval (Results 1 – 25 of 31) sorted by relevance

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/titanic_41/usr/src/lib/libfru/libfruraw/
H A Dcrcutils.c119 uint32_t regval = 0; in compute_checksum32() local
130 if (next4bytes > UINT32_T_MAX - regval) { in compute_checksum32()
131 next4bytes -= UINT32_T_MAX - regval; in compute_checksum32()
132 regval = 0; in compute_checksum32()
136 regval += next4bytes; in compute_checksum32()
150 if (next4bytes > UINT32_T_MAX - regval) { in compute_checksum32()
151 next4bytes -= UINT32_T_MAX - regval; in compute_checksum32()
152 regval = 0; in compute_checksum32()
154 regval += next4bytes; in compute_checksum32()
156 return ((uint32_t)regval); in compute_checksum32()
/titanic_41/usr/src/cmd/picl/plugins/sun4u/lib/fruaccess/
H A Dcrcutils.c121 uint32_t regval = 0; in compute_checksum32() local
132 if (next4bytes > UINT32_T_MAX - regval) { in compute_checksum32()
133 next4bytes -= UINT32_T_MAX - regval; in compute_checksum32()
134 regval = 0; in compute_checksum32()
138 regval += next4bytes; in compute_checksum32()
152 if (next4bytes > UINT32_T_MAX - regval) { in compute_checksum32()
153 next4bytes -= UINT32_T_MAX - regval; in compute_checksum32()
154 regval = 0; in compute_checksum32()
156 regval += next4bytes; in compute_checksum32()
158 return ((uint32_t)regval); in compute_checksum32()
/titanic_41/usr/src/uts/common/io/rge/
H A Drge_chip.c82 uint32_t regval; in rge_reg_set32() local
87 regval = rge_reg_get32(rgep, regno); in rge_reg_set32()
88 regval |= bits; in rge_reg_set32()
89 rge_reg_put32(rgep, regno, regval); in rge_reg_set32()
98 uint32_t regval; in rge_reg_clr32() local
103 regval = rge_reg_get32(rgep, regno); in rge_reg_clr32()
104 regval &= ~bits; in rge_reg_clr32()
105 rge_reg_put32(rgep, regno, regval); in rge_reg_clr32()
162 uint8_t regval; in rge_reg_set8() local
167 regval = rge_reg_get8(rgep, regno); in rge_reg_set8()
[all …]
/titanic_41/usr/src/uts/common/io/bge/
H A Dbge_chip2.c182 uint16_t regval; in bge_cfg_clr16() local
187 regval = pci_config_get16(bgep->cfg_handle, regno); in bge_cfg_clr16()
190 (void *)bgep, regno, bits, regval, regval & ~bits)); in bge_cfg_clr16()
192 regval &= ~bits; in bge_cfg_clr16()
193 pci_config_put16(bgep->cfg_handle, regno, regval); in bge_cfg_clr16()
204 uint32_t regval; in bge_cfg_clr32() local
209 regval = pci_config_get32(bgep->cfg_handle, regno); in bge_cfg_clr32()
212 (void *)bgep, regno, bits, regval, regval & ~bits)); in bge_cfg_clr32()
214 regval &= ~bits; in bge_cfg_clr32()
215 pci_config_put32(bgep->cfg_handle, regno, regval); in bge_cfg_clr32()
[all …]
H A Dbge_mii.c1786 uint32_t regval; in bge_phys_init() local
1802 regval = bge_reg_get32(bgep, SGMII_STATUS_REG); in bge_phys_init()
1803 if (regval & MEDIA_SELECTION_MODE) in bge_phys_init()
/titanic_41/usr/src/uts/sun4v/promif/
H A Dpromif_io.c319 char *regval; in promif_instance_to_path() local
350 regval = kmem_zalloc(rlen, KM_SLEEP); in promif_instance_to_path()
352 (void) prom_getprop(node, OBP_REG, regval); in promif_instance_to_path()
354 csaddr = (uint_t *)regval; in promif_instance_to_path()
359 kmem_free(regval, rlen); in promif_instance_to_path()
/titanic_41/usr/src/uts/common/io/ixgbe/
H A Dixgbe_82598.c246 u32 regval; in ixgbe_start_hw_82598() local
257 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); in ixgbe_start_hw_82598()
258 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; in ixgbe_start_hw_82598()
259 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval); in ixgbe_start_hw_82598()
264 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); in ixgbe_start_hw_82598()
265 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | in ixgbe_start_hw_82598()
267 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); in ixgbe_start_hw_82598()
1315 u32 regval; in ixgbe_enable_relaxed_ordering_82598() local
1323 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); in ixgbe_enable_relaxed_ordering_82598()
1324 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN; in ixgbe_enable_relaxed_ordering_82598()
[all …]
H A Dixgbe_82599.h63 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval);
H A Dixgbe_common.c369 u32 regval; in ixgbe_start_hw_gen2() local
380 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); in ixgbe_start_hw_gen2()
381 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; in ixgbe_start_hw_gen2()
382 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); in ixgbe_start_hw_gen2()
386 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); in ixgbe_start_hw_gen2()
387 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | in ixgbe_start_hw_gen2()
389 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); in ixgbe_start_hw_gen2()
2948 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) in ixgbe_enable_rx_dma_generic() argument
2952 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval); in ixgbe_enable_rx_dma_generic()
3857 u32 regval; in ixgbe_enable_relaxed_ordering_gen2() local
[all …]
H A Dixgbe_common.h99 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval);
H A Dixgbe_api.c1139 s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval) in ixgbe_enable_rx_dma() argument
1142 (hw, regval), IXGBE_NOT_IMPLEMENTED); in ixgbe_enable_rx_dma()
H A Dixgbe_api.h135 s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval);
/titanic_41/usr/src/uts/common/io/nge/
H A Dnge_chip.c114 uint64_t regval; in nge_chip_peek_cfg() local
125 regval = pci_config_get8(ngep->cfg_handle, regno); in nge_chip_peek_cfg()
129 regval = pci_config_get16(ngep->cfg_handle, regno); in nge_chip_peek_cfg()
133 regval = pci_config_get32(ngep->cfg_handle, regno); in nge_chip_peek_cfg()
137 regval = pci_config_get64(ngep->cfg_handle, regno); in nge_chip_peek_cfg()
140 ppd->pp_acc_data = regval; in nge_chip_peek_cfg()
150 uint64_t regval; in nge_chip_poke_cfg() local
158 regval = ppd->pp_acc_data; in nge_chip_poke_cfg()
162 pci_config_put8(ngep->cfg_handle, regno, regval); in nge_chip_poke_cfg()
166 pci_config_put16(ngep->cfg_handle, regno, regval); in nge_chip_poke_cfg()
[all …]
/titanic_41/usr/src/uts/sun4u/io/pci/
H A Ddb21554.c944 uint16_t regval; in db_enable_io() local
1075 regval = pci_config_get16(dbp->conf_handle, (off_t)DB_CONF_CONF_CSR); in db_enable_io()
1078 regval); in db_enable_io()
1080 if (!(regval & enable)) { in db_enable_io()
1082 regval |= enable; in db_enable_io()
1084 regval); in db_enable_io()
1085 regval = pci_config_get16(dbp->conf_handle, in db_enable_io()
1089 regval); in db_enable_io()
1094 regval = ddi_get16(dbp->csr_mem_handle, in db_enable_io()
1098 regval); in db_enable_io()
[all …]
/titanic_41/usr/src/lib/libprtdiag_psr/sparc/desktop/common/
H A Ddesktop.c445 char *name, *model, *compat, *regval; in display_dev_node() local
456 regval = get_prop_val(find_prop(np, "reg")); in display_dev_node()
458 if (!regval) in display_dev_node()
461 reghi = *(int *)regval; in display_dev_node()
/titanic_41/usr/src/cmd/biosdev/
H A Dbiosdev.c214 uint32_t regval; in i_match_pcibdf() local
242 regval = regbuf[0]; in i_match_pcibdf()
244 busnum = PCI_REG_BUS_G(regval); in i_match_pcibdf()
245 devicenum = PCI_REG_DEV_G(regval); in i_match_pcibdf()
246 funcnum = PCI_REG_FUNC_G(regval); in i_match_pcibdf()
/titanic_41/usr/src/uts/common/io/e1000api/
H A De1000_ich8lan.c152 u16 regval; member
165 u16 regval; member
176 u16 regval; member
3340 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS); in e1000_flash_cycle_init_ich8lan()
3351 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); in e1000_flash_cycle_init_ich8lan()
3367 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); in e1000_flash_cycle_init_ich8lan()
3376 hsfsts.regval = E1000_READ_FLASH_REG16(hw, in e1000_flash_cycle_init_ich8lan()
3390 hsfsts.regval); in e1000_flash_cycle_init_ich8lan()
3415 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL); in e1000_flash_cycle_ich8lan()
3418 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); in e1000_flash_cycle_ich8lan()
[all …]
/titanic_41/usr/src/uts/common/sys/nxge/
H A Dnxge_mac_hw.h2513 #define NXGE_VAL_GET(fieldname, regval) \ argument
2514 (((regval) & ((fieldname) ## _MASK)) >> ((fieldname) ## _SHIFT))
2516 #define NXGE_VAL_SET(fieldname, regval, val) \ argument
2518 (regval) &= ~((fieldname) ## _MASK); \
2519 (regval) |= ((val) << (fieldname ## _SHIFT)); \
/titanic_41/usr/src/cmd/picl/plugins/sun4u/taco/envd/
H A Dpiclenvd.c209 #define TMIN(regval) (((regval & TMIN_MASK) >> TMIN_SHIFT) * TMIN_UNITS) argument
210 #define TRANGE(regval) (regval & TRANGE_MASK) argument
/titanic_41/usr/src/uts/common/io/dmfe/
H A Ddmfe_main.c2445 uint32_t regval; in dmfe_config_init() local
2461 regval = pci_config_get32(handle, PCI_CONF_COMM); in dmfe_config_init()
2462 pci_config_put32(handle, PCI_CONF_COMM, (regval | PCI_COMM_ME)); in dmfe_config_init()
2464 regval = pci_config_get32(handle, PCI_DMFE_CONF_CFDD); in dmfe_config_init()
2466 regval & ~(CFDD_SLEEP | CFDD_SNOOZE)); in dmfe_config_init()
/titanic_41/usr/src/uts/sparc/dtrace/
H A Ddtrace_asm.s242 dtrace_fish(int aframes, int reg, uintptr_t *regval)
/titanic_41/usr/src/uts/common/io/sata/adapters/si3124/
H A Dsi3124.c3340 uint32_t *regval) in si_read_portmult_reg() argument
3440 *regval = (GET_FIS_SECTOR_COUNT(prb->prb_fis) & 0xff) | in si_read_portmult_reg()
3461 uint32_t regval) in si_write_portmult_reg() argument
3475 port, pmport, regnum, regval); in si_write_portmult_reg()
3494 SET_FIS_SECTOR_COUNT(prb->prb_fis, regval & 0xff); in si_write_portmult_reg()
3495 SET_FIS_SECTOR(prb->prb_fis, (regval >> 8) & 0xff); in si_write_portmult_reg()
3496 SET_FIS_CYL_LOW(prb->prb_fis, (regval >> 16) & 0xff); in si_write_portmult_reg()
3497 SET_FIS_CYL_HI(prb->prb_fis, (regval >> 24) & 0xff); in si_write_portmult_reg()
/titanic_41/usr/src/cmd/picl/plugins/sun4u/enchilada/envd/
H A Dpiclenvd.c285 #define TMIN(regval) (((regval & TMIN_MASK) >> TMIN_SHIFT) * TMIN_UNITS) argument
286 #define TRANGE(regval) (regval & TRANGE_MASK) argument
/titanic_41/usr/src/uts/common/io/arn/
H A Darn_hw.c1585 uint32_t regval; in ath9k_hw_set_dma() local
1587 regval = REG_READ(ah, AR_AHB_MODE); in ath9k_hw_set_dma()
1588 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN); in ath9k_hw_set_dma()
1590 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK; in ath9k_hw_set_dma()
1591 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B); in ath9k_hw_set_dma()
1595 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK; in ath9k_hw_set_dma()
1596 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B); in ath9k_hw_set_dma()
/titanic_41/usr/src/cmd/picl/plugins/common/devtree/
H A Dpicldevtree.c2939 get_first_reg_word(picl_nodehdl_t nodeh, uint32_t *regval) in get_first_reg_word() argument
2960 *regval = *regbuf; /* get first 32-bit value */ in get_first_reg_word()
2971 uint32_t regval; in get_device_id() local
2973 err = get_first_reg_word(nodeh, &regval); in get_device_id()
2977 *dev_id = PCI_DEVICE_ID(regval); in get_device_id()

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