Home
last modified time | relevance | path

Searched refs:regp (Results 1 – 25 of 48) sorted by relevance

12

/titanic_41/usr/src/uts/common/io/cpqary3/
H A Dcpqary3.h168 #define DDI_GET8(ctlr, regp) \ argument
169 ddi_get8((ctlr)->ct_handle, (uint8_t *)(regp))
170 #define DDI_PUT8(ctlr, regp, value) \ argument
171 ddi_put8((ctlr)->ct_handle, (uint8_t *)(regp), (value))
172 #define DDI_GET16(ctlr, regp) \ argument
173 ddi_get16((ctlr)->ct_handle, (uint16_t *)(regp))
174 #define DDI_PUT16(ctlr, regp, value) \ argument
175 ddi_put16((ctlr)->ct_handle, (uint16_t *)(regp), (value))
176 #define DDI_GET32(ctlr, regp) \ argument
177 ddi_get32((ctlr)->ct_handle, (uint32_t *)(regp))
[all …]
H A Dcpqary3.c761 uint32_t *regp; in cpqary3_update_ctlrdetails() local
796 "reg", (caddr_t)&regp, &reglen) != DDI_PROP_SUCCESS) in cpqary3_update_ctlrdetails()
799 cpqary3p->bus = PCI_REG_BUS_G(*regp); in cpqary3_update_ctlrdetails()
800 cpqary3p->dev = PCI_REG_DEV_G(*regp); in cpqary3_update_ctlrdetails()
801 cpqary3p->fun = PCI_REG_FUNC_G(*regp); in cpqary3_update_ctlrdetails()
804 if (PCI_REG_ADDR_G(*(regp + regset_index * 5)) == 0x2) { in cpqary3_update_ctlrdetails()
819 if (PCI_REG_ADDR_G(*(regp + regset_index * 5)) == 0x3) { in cpqary3_update_ctlrdetails()
833 MEM_SFREE(regp, reglen); in cpqary3_update_ctlrdetails()
/titanic_41/usr/src/cmd/rpcbind/
H A Drpcb_svc_com.c105 rpcbproc_set_com(RPCB *regp, bool_t *result, struct svc_req *rqstp, in rpcbproc_set_com() argument
110 *result = map_set(regp, getowner(rqstp->rq_xprt, owner)); in rpcbproc_set_com()
118 map_set(RPCB *regp, char *owner) in map_set() argument
132 fnd = find_service(regp->r_prog, regp->r_vers, regp->r_netid); in map_set()
133 if (fnd && (fnd->rpcb_map.r_vers == regp->r_vers)) { in map_set()
134 if (strcmp(fnd->rpcb_map.r_addr, regp->r_addr) == 0) { in map_set()
159 delete_prog(regp->r_prog); in map_set()
176 a->r_prog = regp->r_prog; in map_set()
177 a->r_vers = regp->r_vers; in map_set()
178 a->r_netid = strdup(regp->r_netid); in map_set()
[all …]
H A Drpcb_svc_4.c225 rpcbproc_getaddrlist(rpcb *regp, rpcb_entry_list_ptr *result, in rpcbproc_getaddrlist() argument
257 prog = regp->r_prog; in rpcbproc_getaddrlist()
258 vers = regp->r_vers; in rpcbproc_getaddrlist()
262 if (*(regp->r_addr) != '\0') { in rpcbproc_getaddrlist()
263 saddr = regp->r_addr; in rpcbproc_getaddrlist()
/titanic_41/usr/src/cmd/sh/
H A Dxec.c474 struct regnod *regp; local
476 regp = swptr(t)->swlst;
477 while (regp)
479 struct argnod *rex = regp->regptr;
487 execute(regp->regcom, XEC_NOSTOP, errorflg);
488 regp = 0;
494 if (regp)
495 regp = regp->regnxt;
H A Dfunc.c183 freereg(struct regnod *regp) in freereg() argument
187 while (regp) in freereg()
189 free_arg(regp->regptr); in freereg()
190 freetree(regp->regcom); in freereg()
191 sav = regp->regnxt; in freereg()
192 free(regp); in freereg()
193 regp = sav; in freereg()
/titanic_41/usr/src/uts/common/io/cxgbe/t4nex/
H A Dadapter.c29 return (ddi_get32(sc->regh, (uint32_t *)(sc->regp + reg))); in t4_read_reg()
36 ddi_put32(sc->regh, (uint32_t *)(sc->regp + reg), val); in t4_write_reg()
79 return (ddi_get64(sc->regh, (uint64_t *)(sc->regp + reg))); in t4_read_reg64()
86 ddi_put64(sc->regh, (uint64_t *)(sc->regp + reg), val); in t4_write_reg64()
/titanic_41/usr/src/uts/common/io/nxge/npi/
H A Dnpi_rx_rd64.h240 (uint64_t *)(handle.regp + (uint32_t)offset)); in RXDMA_REG_READ64()
242 *value = ddi_get64(handle.regh, (uint64_t *)(handle.regp + offset)); in RXDMA_REG_READ64()
H A Dnpi_rx_wr64.h218 (uint64_t *)(handle.regp + (uint32_t)offset), value); in RXDMA_REG_WRITE64()
221 (uint64_t *)(handle.regp + offset), value); in RXDMA_REG_WRITE64()
H A Dnpi_tx_rd64.h140 (uint64_t *)(handle.regp + (uint32_t)offset)); in TXDMA_REG_READ64()
142 *value = ddi_get64(handle.regh, (uint64_t *)(handle.regp + offset)); in TXDMA_REG_READ64()
H A Dnpi_tx_wr64.h140 (uint64_t *)(handle.regp + (uint32_t)offset), value); in TXDMA_REG_WRITE64()
143 (uint64_t *)(handle.regp + offset), value); in TXDMA_REG_WRITE64()
H A Dnpi_rx_rd32.h126 return (ddi_get32(handle.regh, (uint32_t *)(handle.regp + offset))); in RXDMA_REG_READ32()
H A Dnpi.h205 npi_reg_ptr_t regp; member
/titanic_41/usr/src/uts/common/io/hxge/
H A Dhxge_send.c315 hpi_desc_handle.regp = (uint32_t)tx_desc_p; in hxge_start()
317 hpi_desc_handle.regp = (uint64_t)tx_desc_p; in hxge_start()
464 hpi_desc_handle.regp = (uint32_t)tx_desc_p; in hxge_start()
466 hpi_desc_handle.regp = (uint64_t)tx_desc_p; in hxge_start()
506 hpi_desc_handle.regp = in hxge_start()
537 hpi_desc_handle.regp = (uint32_t)tx_desc_p; in hxge_start()
539 hpi_desc_handle.regp = (uint64_t)tx_desc_p; in hxge_start()
610 hpi_desc_handle.regp = (uint32_t)tx_desc_p; in hxge_start()
612 hpi_desc_handle.regp = (uint64_t)tx_desc_p; in hxge_start()
805 hpi_handle.regp = (uint32_t)tx_desc_p; in hxge_start()
[all …]
H A Dhxge_impl.h101 #define HPI_PCI_ADD_HANDLE_SET(hxgep, ap) (hxgep->hpi_pci_handle.regp = ap)
109 hxgep->hpi_handle.regp = ap;
117 hxgep->hpi_reg_handle.regp = ap;
125 hxgep->hpi_msi_handle.regp = ap;
H A Dhpi.h155 hpi_reg_ptr_t regp; member
/titanic_41/usr/src/uts/common/sys/nxge/
H A Dnxge_impl.h158 #define NPI_PCI_ADD_HANDLE_SET(nxgep, ap) (nxgep->npi_pci_handle.regp = ap)
166 nxgep->npi_handle.regp = ap;
174 nxgep->npi_reg_handle.regp = ap;
177 #define NPI_MSI_ADD_HANDLE_SET(nxgep, ap) (nxgep->npi_msi_handle.regp = ap)
185 nxgep->npi_vreg_handle.regp = ap;
193 nxgep->npi_v2reg_handle.regp = ap;
196 #define NPI_PCI_ADD_HANDLE_GET(nxgep) (nxgep->npi_pci_handle.regp)
198 #define NPI_ADD_HANDLE_GET(nxgep) (nxgep->npi_handle.regp)
200 #define NPI_REG_ADD_HANDLE_GET(nxgep) (nxgep->npi_reg_handle.regp)
202 #define NPI_MSI_ADD_HANDLE_GET(nxgep) (nxgep->npi_msi_handle.regp)
[all …]
/titanic_41/usr/src/uts/i86pc/io/acpi/acpidev/
H A Dacpidev_resource.c116 acpidev_phys_spec_t *regp; in acpidev_resource_handle_grow() local
120 sz = sizeof (*regp) * rhdl->acpidev_reg_max; in acpidev_resource_handle_grow()
121 regp = kmem_zalloc(sz, KM_SLEEP); in acpidev_resource_handle_grow()
122 sz = sizeof (*regp) * rhdl->acpidev_reg_count; in acpidev_resource_handle_grow()
123 bcopy(rhdl->acpidev_regp, regp, sz); in acpidev_resource_handle_grow()
127 rhdl->acpidev_regp = regp; in acpidev_resource_handle_grow()
163 acpidev_regspec_t *regp) in acpidev_resource_insert_reg() argument
166 ASSERT(regp != NULL); in acpidev_resource_insert_reg()
171 rhdl->acpidev_regp[rhdl->acpidev_reg_count] = *regp; in acpidev_resource_insert_reg()
179 uint_t mask, uint_t value, acpidev_regspec_t *regp, uint_t *cntp) in acpidev_resource_get_regs() argument
[all …]
/titanic_41/usr/src/cmd/mdb/intel/kmdb/
H A Dkaif.c236 kreg_t *regp; in kaif_get_register() local
238 if ((regp = kaif_find_regp(regname)) == NULL) in kaif_get_register()
241 *valp = *regp; in kaif_get_register()
249 kreg_t *regp; in kaif_set_register() local
251 if ((regp = kaif_find_regp(regname)) == NULL) in kaif_set_register()
254 *regp = val; in kaif_set_register()
/titanic_41/usr/src/uts/i86pc/sys/
H A Dacpidev_rsc.h148 acpidev_regspec_t *regp);
150 uint_t mask, uint_t value, acpidev_regspec_t *regp, uint_t *cntp);
/titanic_41/usr/src/uts/sun4u/io/
H A Disadma.c627 ebus_regspec_t *child_regp, *regp; in isadma_map() local
637 "reg", (caddr_t)&regp, &reglen) != DDI_SUCCESS) { in isadma_map()
641 child_regp = regp + rnumber; in isadma_map()
645 (void *)isadmap->isadma_regp, (void *)regp)); in isadma_map()
702 kmem_free(regp, reglen); in isadma_map()
H A Dpmubus.c589 pmubus_regspec_t *regp, pci_regspec_t *pci_regp) in pmubus_apply_range() argument
598 addr = regp->reg_addr & ~MAPPING_SHARED_BITS_MASK; in pmubus_apply_range()
603 ((addr + regp->reg_size) <= in pmubus_apply_range()
618 pci_regp->pci_size_low = MIN(regp->reg_size, rangep->rng_size); in pmubus_apply_range()
623 if (regp->reg_addr & MAPPING_SHARED_BITS_MASK) in pmubus_apply_range()
/titanic_41/usr/src/cmd/mdb/sparc/kmdb/
H A Dkaif.c250 kreg_t *regp; in kaif_get_register() local
259 if ((regp = kaif_find_regp(save, regname)) == NULL) in kaif_get_register()
262 *valp = *regp; in kaif_get_register()
271 kreg_t *regp; in kaif_set_register() local
285 if ((regp = kaif_find_regp(save, regname)) == NULL) in kaif_set_register()
288 *regp = val; in kaif_set_register()
/titanic_41/usr/src/uts/common/io/nxge/
H A Dnxge_send.c487 npi_desc_handle.regp = (uint32_t)tx_desc_p; in nxge_start()
489 npi_desc_handle.regp = (uint64_t)tx_desc_p; in nxge_start()
658 npi_desc_handle.regp = (uint32_t)tx_desc_p; in nxge_start()
660 npi_desc_handle.regp = (uint64_t)tx_desc_p; in nxge_start()
709 npi_desc_handle.regp = in nxge_start()
712 npi_desc_handle.regp = in nxge_start()
749 npi_desc_handle.regp = (uint32_t)tx_desc_p; in nxge_start()
751 npi_desc_handle.regp = (uint64_t)tx_desc_p; in nxge_start()
838 npi_desc_handle.regp = (uint32_t)tx_desc_p; in nxge_start()
840 npi_desc_handle.regp = (uint64_t)tx_desc_p; in nxge_start()
[all …]
/titanic_41/usr/src/uts/i86pc/io/amd_iommu/
H A Damd_iommu_impl.h475 extern uint64_t amd_iommu_reg_get64_workaround(uint64_t *regp, uint32_t bits);
476 extern uint64_t amd_iommu_reg_set64_workaround(uint64_t *regp, uint32_t bits,

12