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Searched refs:reg_val (Results 1 – 25 of 28) sorted by relevance

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/titanic_41/usr/src/uts/common/io/ixgbe/
H A Dixgbe_debug.c430 uint32_t reg_val, hw_index; in ixgbe_dump_regs() local
437 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL); in ixgbe_dump_regs()
438 ixgbe_log(ixgbe, "\tCTRL=%x\n", reg_val); in ixgbe_dump_regs()
439 reg_val = IXGBE_READ_REG(hw, IXGBE_STATUS); in ixgbe_dump_regs()
440 ixgbe_log(ixgbe, "\tSTATUS=%x\n", reg_val); in ixgbe_dump_regs()
441 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); in ixgbe_dump_regs()
442 ixgbe_log(ixgbe, "\tCTRL_EXT=%x\n", reg_val); in ixgbe_dump_regs()
443 reg_val = IXGBE_READ_REG(hw, IXGBE_FCTRL); in ixgbe_dump_regs()
444 ixgbe_log(ixgbe, "\tFCTRL=%x\n", reg_val); in ixgbe_dump_regs()
449 reg_val = IXGBE_READ_REG(hw, IXGBE_GPIE); in ixgbe_dump_regs()
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H A Dixgbe_main.c2147 uint32_t reg_val; in ixgbe_setup_rx_ring() local
2191 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rx_ring->hw_index)); in ixgbe_setup_rx_ring()
2192 reg_val |= IXGBE_RXDCTL_ENABLE; /* enable queue */ in ixgbe_setup_rx_ring()
2196 reg_val |= 0x0020; /* pthresh */ in ixgbe_setup_rx_ring()
2198 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rx_ring->hw_index), reg_val); in ixgbe_setup_rx_ring()
2202 reg_val = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); in ixgbe_setup_rx_ring()
2203 reg_val |= (IXGBE_RDRXCTL_CRCSTRIP | IXGBE_RDRXCTL_AGGDIS); in ixgbe_setup_rx_ring()
2204 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg_val); in ixgbe_setup_rx_ring()
2211 reg_val = (ixgbe->rx_buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) | in ixgbe_setup_rx_ring()
2213 reg_val |= IXGBE_SRRCTL_DROP_EN; in ixgbe_setup_rx_ring()
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H A Dixgbe_gld.c101 uint32_t reg_val; in ixgbe_m_promisc() local
110 reg_val = IXGBE_READ_REG(hw, IXGBE_FCTRL); in ixgbe_m_promisc()
113 reg_val |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); in ixgbe_m_promisc()
115 reg_val &= (~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE)); in ixgbe_m_promisc()
117 IXGBE_WRITE_REG(&ixgbe->hw, IXGBE_FCTRL, reg_val); in ixgbe_m_promisc()
/titanic_41/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/
H A Dlm_hw_access.c412 u32_t reg_val = 0; in lm_gpio_read() local
491 reg_val = REG_RD(pdev, MISC_REG_GPIO); in lm_gpio_read()
492 DbgMessage(NULL, INFORM, "lm_gpio_read: MISC_REG_GPIO value 0x%x mask 0x%x\n", reg_val, mask); in lm_gpio_read()
495 if ((reg_val & mask) == mask) in lm_gpio_read()
734 u32_t reg_val = 0, mask = 0; in lm_spio_read() local
737 reg_val = REG_RD(pdev, MISC_REG_SPIO); in lm_spio_read()
739 DbgMessage(pdev, INFORM, "lm_spio_read: MISC_REG_SPIO value is 0x%x\n", reg_val); in lm_spio_read()
756 reg_val |= (MISC_SPIO_SPIO4 << MISC_SPIO_FLOAT_POS); in lm_spio_read()
760 reg_val |= (MISC_SPIO_SPIO5 << MISC_SPIO_FLOAT_POS); in lm_spio_read()
764 reg_val |= (MISC_SPIO_UMP_ADDR0 << MISC_SPIO_FLOAT_POS); in lm_spio_read()
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/titanic_41/usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/
H A Decore_init.h200 u32 reg_val; in ecore_set_mcp_parity() local
203 reg_val = REG_RD(pdev, mcp_attn_ctl_regs[i].addr); in ecore_set_mcp_parity()
206 reg_val |= MISC_AEU_ENABLE_MCP_PRTY_BITS; /* Linux is using mcp_attn_ctl_regs[i].bits */ in ecore_set_mcp_parity()
208 reg_val &= ~MISC_AEU_ENABLE_MCP_PRTY_BITS; /* Linux is using mcp_attn_ctl_regs[i].bits */ in ecore_set_mcp_parity()
210 REG_WR(pdev, mcp_attn_ctl_regs[i].addr, reg_val); in ecore_set_mcp_parity()
252 u32 reg_val, mcp_aeu_bits = in ecore_clear_blocks_parity() local
268 reg_val = REG_RD(pdev, ecore_blocks_parity_data[i]. in ecore_clear_blocks_parity()
270 if (reg_val & reg_mask) { in ecore_clear_blocks_parity()
274 reg_val & reg_mask); in ecore_clear_blocks_parity()
280 reg_val = REG_RD(pdev, MISC_REG_AEU_AFTER_INVERT_4_MCP); in ecore_clear_blocks_parity()
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/titanic_41/usr/src/uts/sun4u/io/i2c/clients/
H A Dadm1026.c440 adm1026_send8(adm1026_unit_t *unitp, uint8_t reg, uint8_t reg_val, in adm1026_send8() argument
449 val |= (reg_val & reg_mask); in adm1026_send8()
484 uint8_t reg_val = 0; in adm1026_get_output() local
488 err = adm1026_get8(unitp, ADM1026_STS_REG5, &reg_val); in adm1026_get_output()
492 *val = reg_val; in adm1026_get_output()
496 err = adm1026_get8(unitp, ADM1026_STS_REG6, &reg_val); in adm1026_get_output()
500 *val |= ((reg_val << OUTPUT_SHIFT) & (mask & 0xff00)); in adm1026_get_output()
636 err = adm1026_set_output(unitp, g_buf.reg_val, g_buf.reg_mask); in adm1026_ioctl()
640 err = adm1026_get_output(unitp, g_buf.reg_mask, &g_buf.reg_val); in adm1026_ioctl()
648 err = adm1026_set_config(unitp, cmd, g_buf.reg_val, in adm1026_ioctl()
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H A Dpca9556.c715 g_buf.reg_val = g_buf.reg_mask & in pca9556_ioctl()
730 (g_buf.reg_val & g_buf.reg_mask); in pca9556_ioctl()
/titanic_41/usr/src/uts/common/io/1394/targets/dcam1394/
H A Ddcam_param.c56 uint_t reg_val);
1705 feature_csr_val_subparam_extract(uint_t subparam, uint_t reg_val) in feature_csr_val_subparam_extract() argument
1712 ret_val = (reg_val & DCAM1394_MASK_PRESENCE_INQ) >> in feature_csr_val_subparam_extract()
1717 ret_val = (reg_val & DCAM1394_MASK_ON_OFF) >> in feature_csr_val_subparam_extract()
1722 ret_val = (reg_val & DCAM1394_MASK_A_M_MODE) >> in feature_csr_val_subparam_extract()
1727 ret_val = (reg_val & DCAM1394_MASK_VALUE) >> in feature_csr_val_subparam_extract()
1732 ret_val = (reg_val & DCAM1394_MASK_U_VALUE) >> in feature_csr_val_subparam_extract()
1738 ret_val = (reg_val & DCAM1394_MASK_V_VALUE) >> in feature_csr_val_subparam_extract()
1760 uint_t reg_val) in feature_elm_inq_reg_val_subparam_extract() argument
1767 ret_val = (reg_val & DCAM1394_MASK_READOUT_INQ) >> in feature_elm_inq_reg_val_subparam_extract()
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/titanic_41/usr/src/lib/libprtdiag_psr/sparc/opl/common/
H A Dopl_picl.c104 int *reg_val; in opl_pci_callback() local
196 reg_val = malloc(pinfo.size); in opl_pci_callback()
197 if (reg_val == NULL) in opl_pci_callback()
202 (nodeh, OBP_PROP_REG, reg_val, pinfo.size); in opl_pci_callback()
205 free(reg_val); in opl_pci_callback()
210 if (reg_val[0] != 0) { in opl_pci_callback()
212 (((reg_val[0]) & PCI_DEV_MASK) >> 11); in opl_pci_callback()
214 (((reg_val[0]) & PCI_FUNC_MASK) >> 8); in opl_pci_callback()
216 (((reg_val[0]) & PCI_BUS_MASK) >> 16); in opl_pci_callback()
218 free(reg_val); in opl_pci_callback()
/titanic_41/usr/src/uts/common/io/e1000api/
H A De1000_i210.c829 u32 wuc, mdicnfg, ctrl, ctrl_ext, reg_val; in e1000_pll_workaround_i210() local
836 reg_val = mdicnfg & ~E1000_MDICNFG_EXT_MDIO; in e1000_pll_workaround_i210()
837 E1000_WRITE_REG(hw, E1000_MDICNFG, reg_val); in e1000_pll_workaround_i210()
865 reg_val = (E1000_INVM_AUTOLOAD << 4) | (tmp_nvm << 16); in e1000_pll_workaround_i210()
866 E1000_WRITE_REG(hw, E1000_EEARBC_I210, reg_val); in e1000_pll_workaround_i210()
874 reg_val = (E1000_INVM_AUTOLOAD << 4) | (nvm_word << 16); in e1000_pll_workaround_i210()
875 E1000_WRITE_REG(hw, E1000_EEARBC_I210, reg_val); in e1000_pll_workaround_i210()
H A De1000_82575.c2260 u32 reg_val, reg_offset; in e1000_vmdq_set_anti_spoofing_pf() local
2274 reg_val = E1000_READ_REG(hw, reg_offset); in e1000_vmdq_set_anti_spoofing_pf()
2276 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK | in e1000_vmdq_set_anti_spoofing_pf()
2281 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS)); in e1000_vmdq_set_anti_spoofing_pf()
2283 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK | in e1000_vmdq_set_anti_spoofing_pf()
2286 E1000_WRITE_REG(hw, reg_offset, reg_val); in e1000_vmdq_set_anti_spoofing_pf()
/titanic_41/usr/src/uts/common/io/e1000g/
H A De1000g_rx.c151 uint32_t reg_val; in e1000g_rx_setup() local
358 reg_val = in e1000g_rx_setup()
362 E1000_WRITE_REG(hw, E1000_RXCSUM, reg_val); in e1000g_rx_setup()
369 reg_val = E1000_READ_REG(hw, E1000_RFCTL); in e1000g_rx_setup()
370 reg_val |= (E1000_RFCTL_IPV6_EX_DIS | in e1000g_rx_setup()
372 E1000_WRITE_REG(hw, E1000_RFCTL, reg_val); in e1000g_rx_setup()
/titanic_41/usr/src/uts/common/io/chxge/
H A Dglue.c90 t1_read_reg_4(ch_t *obj, uint32_t reg_val) in t1_read_reg_4() argument
92 return (ddi_get32(obj->ch_hbar0, (uint32_t *)(obj->ch_bar0 + reg_val))); in t1_read_reg_4()
96 t1_write_reg_4(ch_t *obj, uint32_t reg_val, uint32_t write_val) in t1_write_reg_4() argument
98 ddi_put32(obj->ch_hbar0, (uint32_t *)(obj->ch_bar0+reg_val), write_val); in t1_write_reg_4()
H A Dch.h285 uint32_t t1_read_reg_4(ch_t *obj, uint32_t reg_val);
286 void t1_write_reg_4(ch_t *obj, uint32_t reg_val, uint32_t write_val);
/titanic_41/usr/src/uts/sun4u/sys/i2c/clients/
H A Di2c_gpio.h49 uint32_t reg_val; member
/titanic_41/usr/src/uts/common/io/
H A Dpci_cap.c206 pci_htcap_locate(ddi_acc_handle_t h, uint16_t reg_mask, uint16_t reg_val, in pci_htcap_locate() argument
235 reg_mask) == reg_val) { in pci_htcap_locate()
/titanic_41/usr/src/uts/common/io/nxge/
H A Dnxge_hio_guest.c180 int *reg_val; in nxge_hio_vr_add() local
206 0, "reg", &reg_val, &reg_len) != DDI_PROP_SUCCESS) { in nxge_hio_vr_add()
211 cookie = (uint32_t)(reg_val[0]); in nxge_hio_vr_add()
212 ddi_prop_free(reg_val); in nxge_hio_vr_add()
/titanic_41/usr/src/uts/common/io/i40e/core/
H A Di40e_common.c1123 u32 reg_val; in i40e_pre_tx_queue_cfg() local
1130 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); in i40e_pre_tx_queue_cfg()
1131 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; in i40e_pre_tx_queue_cfg()
1132 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); in i40e_pre_tx_queue_cfg()
1135 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; in i40e_pre_tx_queue_cfg()
1137 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; in i40e_pre_tx_queue_cfg()
1139 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); in i40e_pre_tx_queue_cfg()
3214 u32 reg_addr, u64 *reg_val, in i40e_aq_debug_read_register() argument
3222 if (reg_val == NULL) in i40e_aq_debug_read_register()
3232 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) | in i40e_aq_debug_read_register()
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H A Di40e_prototype.h111 u32 reg_addr, u64 reg_val,
114 u32 reg_addr, u64 *reg_val,
498 u32 reg_addr, u32 *reg_val,
502 u32 reg_addr, u32 reg_val,
504 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val);
/titanic_41/usr/src/uts/common/io/nxge/npi/
H A Dnpi_espc.c362 uint32_t reg_val = 0; in npi_espc_reg_get() local
365 reg_val = val & 0xffffffff; in npi_espc_reg_get()
367 return (reg_val); in npi_espc_reg_get()
/titanic_41/usr/src/cmd/picl/plugins/sun4u/mpxu/frudr/
H A Dpiclfrudr.c647 gpio.reg_val = (leds ^ 0xff); in solaris_setleds()
650 gpio.reg_val = (leds ^ 0xff); in solaris_setleds()
691 gpio.reg_val = BOSTON_FRONT_CLEAR_POL; in boston_set_frontleds()
699 gpio.reg_val = BOSTON_FRONT_CLEAR_DIR; in boston_set_frontleds()
707 gpio.reg_val = leds; in boston_set_frontleds()
728 gpio.reg_val = BOSTON_REAR_CLEAR_POL; in boston_set_rearleds()
736 gpio.reg_val = BOSTON_REAR_LED_MASK; in boston_set_rearleds()
744 gpio.reg_val = leds; in boston_set_rearleds()
/titanic_41/usr/src/uts/common/io/igb/
H A Digb_gld.c478 uint32_t reg_val; in igb_m_promisc() local
487 reg_val = E1000_READ_REG(&igb->hw, E1000_RCTL); in igb_m_promisc()
490 reg_val |= (E1000_RCTL_UPE | E1000_RCTL_MPE); in igb_m_promisc()
492 reg_val &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); in igb_m_promisc()
494 E1000_WRITE_REG(&igb->hw, E1000_RCTL, reg_val); in igb_m_promisc()
H A Digb_main.c2285 uint32_t reg_val; in igb_setup_tx_ring() local
2338 reg_val = E1000_READ_REG(hw, in igb_setup_tx_ring()
2340 reg_val &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN; in igb_setup_tx_ring()
2342 E1000_DCA_TXCTRL(tx_ring->index), reg_val); in igb_setup_tx_ring()
2360 reg_val = E1000_READ_REG(hw, E1000_TXDCTL(tx_ring->index)); in igb_setup_tx_ring()
2361 reg_val |= E1000_TXDCTL_QUEUE_ENABLE; in igb_setup_tx_ring()
2362 E1000_WRITE_REG(hw, E1000_TXDCTL(tx_ring->index), reg_val); in igb_setup_tx_ring()
2375 uint32_t reg_val; in igb_setup_tx() local
2386 reg_val = E1000_READ_REG(hw, E1000_TCTL); in igb_setup_tx()
2387 reg_val &= ~E1000_TCTL_CT; in igb_setup_tx()
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/titanic_41/usr/src/uts/common/sys/
H A Dpci_cap.h39 int pci_htcap_locate(ddi_acc_handle_t h, uint16_t reg_mask, uint16_t reg_val,
/titanic_41/usr/src/uts/common/io/bnxe/577xx/common/
H A Dbnxe_clc.c5673 u16 reg_val; in elink_set_autoneg() local
5678 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val); in elink_set_autoneg()
5682 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN; in elink_set_autoneg()
5684 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | in elink_set_autoneg()
5689 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); in elink_set_autoneg()
5695 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val); in elink_set_autoneg()
5696 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN | in elink_set_autoneg()
5698 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE; in elink_set_autoneg()
5700 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; in elink_set_autoneg()
5702 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; in elink_set_autoneg()
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