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Searched refs:reg_addr (Results 1 – 25 of 27) sorted by relevance

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/titanic_41/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/fw/
H A Dbnxe_fw_funcs.c48 u32_t reg_addr, reg_bit_map, vnic; in ecore_map_q_cos() local
69 reg_addr = ECORE_VOQ_Q_REG_ADDR(curr_cos, pf_q_num); in ecore_map_q_cos()
70 reg_bit_map = REG_RD(pdev, reg_addr); in ecore_map_q_cos()
71 REG_WR(pdev, reg_addr, reg_bit_map & (~q_bit_map)); in ecore_map_q_cos()
74 reg_addr = ECORE_VOQ_Q_REG_ADDR(new_cos, pf_q_num); in ecore_map_q_cos()
75 reg_bit_map = REG_RD(pdev, reg_addr); in ecore_map_q_cos()
76 REG_WR(pdev, reg_addr, reg_bit_map | q_bit_map); in ecore_map_q_cos()
81 reg_addr = ECORE_Q_CMDQ_REG_ADDR(pf_q_num); in ecore_map_q_cos()
82 reg_bit_map = REG_RD(pdev, reg_addr); in ecore_map_q_cos()
87 REG_WR(pdev, reg_addr, reg_bit_map); in ecore_map_q_cos()
/titanic_41/usr/src/uts/sun4u/io/
H A Diocache.c185 volatile uint64_t *reg_addr; in sync_stream_buf() local
191 for (i = 0, reg_addr = softsp->str_buf_pg_tag_diag; in sync_stream_buf()
192 i < STREAM_CACHE_LINES; i++, reg_addr++) { in sync_stream_buf()
195 reg = *reg_addr; in sync_stream_buf()
204 (void *)reg_addr, hi, lo)); in sync_stream_buf()
H A Dpmubus.c598 addr = regp->reg_addr & ~MAPPING_SHARED_BITS_MASK; in pmubus_apply_range()
623 if (regp->reg_addr & MAPPING_SHARED_BITS_MASK) in pmubus_apply_range()
709 pmubus_rp.reg_addr = ((uint64_t) in pmubus_map()
744 if ((pmubus_rp.reg_addr + off) > in pmubus_map()
745 (pmubus_rp.reg_addr + pmubus_rp.reg_size)) { in pmubus_map()
750 pmubus_rp.reg_addr += off; in pmubus_map()
776 pmubus_mapreqp->mapreq_addr = pmubus_rp.reg_addr; in pmubus_map()
/titanic_41/usr/src/uts/common/io/chxge/com/
H A Dcphy.h36 int reg_addr, unsigned int *val);
38 int reg_addr, unsigned int val);
93 int reg_addr, unsigned int *val);
95 int reg_addr, unsigned int val);
H A Dch_subr.c277 int reg_addr, unsigned int *val) in fpga_mdio_read() argument
289 V_MI0_PHY_REG_ADDR(reg_addr) | V_MI0_PHY_ADDR(phy_addr)); in fpga_mdio_read()
296 int reg_addr, unsigned int val) in fpga_mdio_write() argument
308 V_MI0_PHY_REG_ADDR(reg_addr) | V_MI0_PHY_ADDR(phy_addr)); in fpga_mdio_write()
360 int reg_addr, unsigned int *valp) in mi1_mdio_read() argument
362 u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr); in mi1_mdio_read()
378 int reg_addr, unsigned int val) in mi1_mdio_write() argument
380 u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr); in mi1_mdio_write()
407 int reg_addr, unsigned int *valp)
415 (void) __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);
[all …]
/titanic_41/usr/src/grub/grub-0.97/netboot/
H A De1000.c110 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
111 static int e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
112 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data);
113 static int e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data);
2814 uint32_t reg_addr, argument
2822 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2824 (uint16_t)reg_addr)))
2828 ret_val = e1000_read_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
2836 uint32_t reg_addr, argument
2845 if(reg_addr > MAX_PHY_REG_ADDRESS) {
[all …]
/titanic_41/usr/src/uts/common/io/ixgbe/
H A Dixgbe_phy.h104 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
106 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
H A Dixgbe_api.c450 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, in ixgbe_read_phy_reg() argument
462 (hw, reg_addr, device_type, phy_data), in ixgbe_read_phy_reg()
476 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, in ixgbe_write_phy_reg() argument
488 (hw, reg_addr, device_type, phy_data), in ixgbe_write_phy_reg()
H A Dixgbe_api.h64 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
66 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
H A Dixgbe_phy.c278 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, in ixgbe_read_phy_reg_generic() argument
299 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | in ixgbe_read_phy_reg_generic()
330 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | in ixgbe_read_phy_reg_generic()
378 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, in ixgbe_write_phy_reg_generic() argument
401 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | in ixgbe_write_phy_reg_generic()
432 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | in ixgbe_write_phy_reg_generic()
/titanic_41/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A Dhw_dump.h242 struct reg_addr { struct
264 static const struct reg_addr reg_addrs[] = { argument
1340 static const struct reg_addr idle_addrs[] = {
1612 static const struct reg_addr split_reg_addrs[] = {
8179 static const struct reg_addr page_read_regs_e1[] = {
8194 static const struct reg_addr page_read_regs_e1h[] = {
8210 static const struct reg_addr page_read_regs_e2[] = {
8225 static const struct reg_addr page_read_regs_e3[] = {
H A Dclc.h24 extern u32 elink_cb_reg_read(struct elink_dev *cb, u32 reg_addr);
25 extern void elink_cb_reg_write(struct elink_dev *cb, u32 reg_addr, u32 val);
/titanic_41/usr/src/uts/sun4u/sys/
H A Dpmubus.h47 uint64_t reg_addr; member
/titanic_41/usr/src/uts/common/io/i40e/core/
H A Di40e_prototype.h111 u32 reg_addr, u64 reg_val,
114 u32 reg_addr, u64 *reg_val,
498 u32 reg_addr, u32 *reg_val,
500 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr);
502 u32 reg_addr, u32 reg_val,
504 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val);
H A Di40e_common.c3214 u32 reg_addr, u64 *reg_val, in i40e_aq_debug_read_register() argument
3227 cmd_resp->address = CPU_TO_LE32(reg_addr); in i40e_aq_debug_read_register()
3249 u32 reg_addr, u64 reg_val, in i40e_aq_debug_write_register() argument
3259 cmd->address = CPU_TO_LE32(reg_addr); in i40e_aq_debug_write_register()
6457 u32 reg_addr, u32 *reg_val, in i40e_aq_rx_ctl_read_register() argument
6470 cmd_resp->address = CPU_TO_LE32(reg_addr); in i40e_aq_rx_ctl_read_register()
6485 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr) in i40e_read_rx_ctl() argument
6495 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL); in i40e_read_rx_ctl()
6505 val = rd32(hw, reg_addr); in i40e_read_rx_ctl()
6521 u32 reg_addr, u32 reg_val, in i40e_aq_rx_ctl_write_register() argument
[all …]
/titanic_41/usr/src/lib/udapl/libdat/include/dat/
H A Dudat_redirection.h59 lmr, lmr_context, rmr_context, reg_len, reg_addr) \ argument
71 (reg_addr))
/titanic_41/usr/src/uts/common/io/audio/drv/audiots/
H A Daudiots.c1151 uint16_t *reg_addr = &state->ts_regs->aud_regs.ap_acrdwr_reg; in audiots_set_ac97() local
1170 if (!(ddi_get16(handle, reg_addr) & in audiots_set_ac97()
1173 ddi_put16(handle, reg_addr, reg); in audiots_set_ac97()
1187 if (!(ddi_get16(handle, reg_addr) & in audiots_set_ac97()
/titanic_41/usr/src/uts/sun4u/io/i2c/nexus/
H A Dsmbus.c737 uint8_t *reg_addr = smbus->smbus_regaddr; in smbus_put() local
741 ddi_put8(hp, &reg_addr[reg], data); in smbus_put()
744 &reg_addr[reg], data)); in smbus_put()
/titanic_41/usr/src/uts/common/io/cxgbe/common/
H A Dt4_regs.h29 #define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr)) argument
32 #define PF0_REG(reg_addr) (PF0_BASE + (reg_addr)) argument
35 #define PF1_REG(reg_addr) (PF1_BASE + (reg_addr)) argument
38 #define PF2_REG(reg_addr) (PF2_BASE + (reg_addr)) argument
41 #define PF3_REG(reg_addr) (PF3_BASE + (reg_addr)) argument
44 #define PF4_REG(reg_addr) (PF4_BASE + (reg_addr)) argument
47 #define PF5_REG(reg_addr) (PF5_BASE + (reg_addr)) argument
50 #define PF6_REG(reg_addr) (PF6_BASE + (reg_addr)) argument
53 #define PF7_REG(reg_addr) (PF7_BASE + (reg_addr)) argument
60 #define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr)) argument
[all …]
/titanic_41/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/
H A Dlm_phy.c75 u32 elink_cb_reg_read(struct elink_dev *cb, u32 reg_addr ) in elink_cb_reg_read() argument
77 return REG_RD(cb, reg_addr); in elink_cb_reg_read()
80 void elink_cb_reg_write(struct elink_dev *cb, u32 reg_addr, u32 val ) in elink_cb_reg_write() argument
82 REG_WR(cb, reg_addr, val); in elink_cb_reg_write()
/titanic_41/usr/src/uts/common/io/bnxe/577xx/hsi/mcp/
H A Dnvm_map.h621 u32_t reg_addr; member
/titanic_41/usr/src/uts/common/io/ntxn/
H A Dniu.c134 address.reg_addr = (unm_crbword_t)reg; in unm_niu_gbe_phy_read()
/titanic_41/usr/src/uts/common/io/e1000api/
H A De1000_ich8lan.c2078 u16 word_addr, reg_data, reg_addr, phy_page = 0; in e1000_sw_lcd_config_ich8lan() local
2164 1, &reg_addr); in e1000_sw_lcd_config_ich8lan()
2169 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { in e1000_sw_lcd_config_ich8lan()
2174 reg_addr &= PHY_REG_MASK; in e1000_sw_lcd_config_ich8lan()
2175 reg_addr |= phy_page; in e1000_sw_lcd_config_ich8lan()
2177 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr, in e1000_sw_lcd_config_ich8lan()
/titanic_41/usr/src/uts/sun4u/io/pci/
H A Dpcisch.c1071 volatile uint64_t *reg_addr = sc_p->sc_ctx_match_reg + ctx; in pci_sc_ctx_inv() local
1074 if (!*reg_addr) { in pci_sc_ctx_inv()
1080 matchreg = *reg_addr; /* re-fetch after 1st flush */ in pci_sc_ctx_inv()
1091 if (pci_ctx_no_compat || !*reg_addr) /* compat: active ctx flush */ in pci_sc_ctx_inv()
/titanic_41/usr/src/uts/common/sys/nxge/
H A Dnxge_mac_hw.h1325 uint32_t reg_addr : 5; member
1335 uint32_t reg_addr : 5;

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