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Searched refs:reg1 (Results 1 – 15 of 15) sorted by relevance

/titanic_41/usr/src/cmd/mdb/sun4u/v9/kmdb/
H A Dmach_asmutil.h38 #define GET_NWIN(scr1, reg1) \ argument
39 rdpr %ver, reg1;\
40 and reg1, VER_MAXWIN, reg1
65 #define SET_PSTATE_COMMON_AG(reg1) \ argument
66 or %g0, PTSTATE_KERN_COMMON | PSTATE_AG, reg1;\
67 wrpr reg1, %pstate
/titanic_41/usr/src/cmd/mdb/sun4v/v9/kmdb/
H A Dmach_asmutil.h38 #define GET_NWIN(scr1, reg1) \ argument
41 rdpr %cwp, reg1; \
74 #define SET_PSTATE_COMMON_AG(reg1) \ argument
75 or %g0, PTSTATE_KERN_COMMON, reg1;\
76 wrpr reg1, %pstate
/titanic_41/usr/src/uts/sun4u/starcat/ml/
H A Ddrmach_asm.s104 #define BUS_SYNC(reg1, reg2) \ argument
106 ldx [reg1], reg2 ;\
108 add reg1, 8, reg1 ;\
114 #define LOAD_MB(cpuid, mb_data, reg1) \ argument
115 set drmach_xt_mb, reg1 ;\
116 ldx [reg1], reg1 ;\
117 add reg1, cpuid, reg1 ;\
118 ldub [reg1], mb_data ;\
119 stub %g0, [reg1]
123 #define SET_LPA(cmd, reg1, reg2) \ argument
[all …]
/titanic_41/usr/src/uts/common/io/rtw/
H A Drtwreg.h1279 #define RTW_BARRIER(regs, reg0, reg1, flags) argument
1291 #define RTW_SYNC(regs, reg0, reg1) \ argument
1292 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_SYNC)
1297 #define RTW_WBW(regs, reg0, reg1) \ argument
1298 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE)
1303 #define RTW_WBR(regs, reg0, reg1) \ argument
1304 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_READ)
1309 #define RTW_RBR(regs, reg0, reg1) \ argument
1310 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_READ_BEFORE_READ)
1315 #define RTW_RBW(regs, reg0, reg1) \ argument
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/titanic_41/usr/src/uts/common/io/hxge/
H A Dhxge_pfc.h119 uint64_t reg1; /* 99:64 */ member
123 uint64_t reg1; /* 99:64 */
226 #define key_reg1 key.regs.reg1
228 #define mask_reg1 mask.regs.reg1
231 #define key1 key.regs.reg1
233 #define mask1 mask.regs.reg1
/titanic_41/usr/src/uts/sun4u/serengeti/ml/
H A Dsbdp_asm.s98 #define GET_ICACHE_PARAMS(reg1, reg2) \ argument
99 GET_CPU_IMPL(reg1) ;\
100 cmp reg1, PANTHER_IMPL ;\
103 set PN_ICACHE_SIZE, reg1 ;\
108 set CH_ICACHE_SIZE, reg1 ;\
/titanic_41/usr/src/common/util/
H A Dgetresponse.c143 yes_no_check(char *ans, regex_t *reg1, regex_t *reg2) in yes_no_check() argument
145 if (regexec(reg1, ans, 0, NULL, 0) == 0) { in yes_no_check()
/titanic_41/usr/src/uts/sun4u/sys/
H A Dcheetahasm.h1104 #define GET_CH_ERR_TL1_PTR(reg1, reg2, offset) \ argument
1105 CPU_INDEX(reg1, reg2); \
1106 sllx reg1, 3, reg1; \
1108 ldx [reg1+reg2], reg1; \
1109 brnz reg1, 1f; \
1110 add reg1, offset, reg1; \
1111 set ch_err_tl1_data, reg1; \
1117 add reg1, reg2, reg1; \
/titanic_41/usr/src/lib/libtnfctl/
H A Dcontinue.c64 prgreg_t reg0, reg1; in tnfctl_continue() local
127 &reg0, &reg1); in tnfctl_continue()
/titanic_41/usr/src/uts/sun4u/cpu/
H A Dopl_olympus_asm.s676 #define OPL_SAVE_GLOBAL(reg1, reg2, reg3) \ argument
677 stxa reg1, [%g0]ASI_SCRATCHPAD ;\
678 mov OPL_SCRATCHPAD_SAVE_AG2, reg1 ;\
679 stxa reg2, [reg1]ASI_SCRATCHPAD ;\
680 mov OPL_SCRATCHPAD_SAVE_AG3, reg1 ;\
681 stxa reg3, [reg1]ASI_SCRATCHPAD
687 #define OPL_RESTORE_GLOBAL(reg1, reg2, reg3) \ argument
688 mov OPL_SCRATCHPAD_SAVE_AG3, reg1 ;\
689 ldxa [reg1]ASI_SCRATCHPAD, reg3 ;\
690 mov OPL_SCRATCHPAD_SAVE_AG2, reg1 ;\
[all …]
H A Dus3_jalapeno_asm.s813 ldxa [%g0]ASI_MCU_CTRL, %o0 ! MCU control reg1 is at offset 0
820 stxa %o0, [%g0]ASI_MCU_CTRL ! MCU control reg1 is at offset 0
/titanic_41/usr/src/uts/common/sys/nxge/
H A Dnxge_fflp_hw.h1184 uint64_t reg1; member
1190 uint64_t reg1;
1254 #define key_reg1 key.regs_e.reg1
1258 #define mask_reg1 mask.regs_e.reg1
1264 #define key1 key.regs_e.reg1
1268 #define mask1 mask.regs_e.reg1
/titanic_41/usr/src/uts/sfmmu/vm/
H A Dhat_sfmmu.h2072 #define SET_KCONTEXTREG(reg0, reg1, reg2, reg3, reg4, label1, label2, label3) argument
2076 #define SET_KCONTEXTREG(reg0, reg1, reg2, reg3, reg4, label1, label2, label3) \ argument
2079 mov MMU_PCONTEXT, reg1; \
2080 ldxa [reg1]ASI_MMU_CTX, reg2; \
2098 stxa reg0, [reg1]ASI_MMU_CTX; \
/titanic_41/usr/src/uts/intel/io/drm/
H A Dradeon_drv.h1033 #define CP_PACKET1(reg0, reg1) \ argument
1034 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
/titanic_41/usr/src/uts/sun4u/ml/
H A Dmach_locore.s1576 ! SET_KCONTEXTREG(reg0, reg1, reg2, reg3, reg4, label1, label2, label3)