/titanic_41/usr/src/uts/common/io/rtw/ |
H A D | rtwreg.h | 1279 #define RTW_BARRIER(regs, reg0, reg1, flags) argument 1291 #define RTW_SYNC(regs, reg0, reg1) \ argument 1292 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_SYNC) 1297 #define RTW_WBW(regs, reg0, reg1) \ argument 1298 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE) 1303 #define RTW_WBR(regs, reg0, reg1) \ argument 1304 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_READ) 1309 #define RTW_RBR(regs, reg0, reg1) \ argument 1310 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_READ_BEFORE_READ) 1315 #define RTW_RBW(regs, reg0, reg1) \ argument [all …]
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/titanic_41/usr/src/uts/common/io/hxge/ |
H A D | hxge_pfc.h | 120 uint64_t reg0; /* 63:0 */ member 122 uint64_t reg0; /* 63:0 */ 225 #define key_reg0 key.regs.reg0 227 #define mask_reg0 mask.regs.reg0 230 #define key0 key.regs.reg0 232 #define mask0 mask.regs.reg0
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/titanic_41/usr/src/lib/libtnfctl/ |
H A D | continue.c | 64 prgreg_t reg0, reg1; in tnfctl_continue() local 127 ®0, ®1); in tnfctl_continue() 132 prexstat = tnfctl_pid_open((pid_t)reg0, in tnfctl_continue()
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/titanic_41/usr/src/uts/common/sys/nxge/ |
H A D | nxge_fflp_hw.h | 1183 uint64_t reg0; member 1191 uint64_t reg0; 1253 #define key_reg0 key.regs_e.reg0 1257 #define mask_reg0 mask.regs_e.reg0 1263 #define key0 key.regs_e.reg0 1267 #define mask0 mask.regs_e.reg0
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/titanic_41/usr/src/uts/sfmmu/vm/ |
H A D | hat_sfmmu.h | 2072 #define SET_KCONTEXTREG(reg0, reg1, reg2, reg3, reg4, label1, label2, label3) argument 2076 #define SET_KCONTEXTREG(reg0, reg1, reg2, reg3, reg4, label1, label2, label3) \ argument 2077 sethi %hi(kcontextreg), reg0; \ 2078 ldx [reg0 + %lo(kcontextreg)], reg0; \ 2081 xor reg0, reg2, reg2; \ 2098 stxa reg0, [reg1]ASI_MMU_CTX; \
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/titanic_41/usr/src/uts/intel/io/drm/ |
H A D | radeon_drv.h | 1033 #define CP_PACKET1(reg0, reg1) \ argument 1034 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
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/titanic_41/usr/src/uts/sun4u/ml/ |
H A D | mach_locore.s | 1576 ! SET_KCONTEXTREG(reg0, reg1, reg2, reg3, reg4, label1, label2, label3)
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