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Searched refs:reg (Results 1 – 25 of 616) sorted by relevance

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/titanic_41/usr/src/uts/common/io/
H A Dvgasubr.c79 vga_get_hardware_settings(struct vgaregmap *reg, int *width, int *height) in vga_get_hardware_settings() argument
81 *width = (GET_HORIZ_END(reg)+1)*8; in vga_get_hardware_settings()
82 *height = GET_VERT_END(reg)+1; in vga_get_hardware_settings()
83 if (GET_VERT_X2(reg)) *height *= 2; in vga_get_hardware_settings()
86 #define PUTB(reg, off, v) ddi_put8(reg->handle, reg->addr + (off), v) argument
87 #define GETB(reg, off) ddi_get8(reg->handle, reg->addr + (off)) argument
90 vga_get_reg(struct vgaregmap *reg, int indexreg) in vga_get_reg() argument
92 return (GETB(reg, indexreg)); in vga_get_reg()
96 vga_set_reg(struct vgaregmap *reg, int indexreg, int v) in vga_set_reg() argument
98 PUTB(reg, indexreg, v); in vga_set_reg()
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H A Dsock_conf.c71 smod_register(const smod_reg_t *reg) in smod_register() argument
79 if (reg->smod_version != SOCKMOD_VERSION || in smod_register()
80 reg->smod_dc_version != SOCK_DC_VERSION || in smod_register()
81 reg->smod_uc_version != SOCK_UC_VERSION) { in smod_register()
84 reg->smod_name); in smod_register()
90 if ((smodp = smod_find(reg->smod_name)) != NULL) { in smod_register()
97 smodp = smod_create(reg->smod_name); in smod_register()
98 smodp->smod_version = reg->smod_version; in smod_register()
103 ASSERT(reg->__smod_priv != NULL); in smod_register()
105 reg->__smod_priv->smodp_sock_create_func; in smod_register()
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/titanic_41/usr/src/uts/intel/io/intel_nhm/
H A Dintel_nhm.h62 #define MC_SCRUB_CONTROL_WR(cpu, reg) nhm_pci_putl(SOCKET_BUS(cpu), 3, 2, \ argument
63 0x4c, reg);
65 #define MC_SSR_CONTROL_WR(cpu, reg) nhm_pci_putl(SOCKET_BUS(cpu), 3, 2, 0x48, \ argument
66 reg);
102 #define MC_CONTROL_CHANNEL_ACTIVE(reg, channel) \ argument
103 ((reg) & (1 << (8 + (channel))) != 0)
104 #define MC_CONTROL_ECCEN(reg) (((reg) >> 1) & 1) argument
105 #define MC_CONTROL_CLOSED_PAGE(reg) ((reg) & 1) argument
106 #define MC_CONTROL_DIVBY3(reg) ((reg >> 6) &1) argument
113 #define CHANNEL_DISABLED(reg, channel) ((reg) & (1 << (channel))) argument
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H A Dnhm_pci_cfg.c45 pci_regspec_t reg; in nhm_pci_cfg_setup() local
48 reg.pci_phys_mid = 0; in nhm_pci_cfg_setup()
49 reg.pci_phys_low = 0; in nhm_pci_cfg_setup()
50 reg.pci_size_hi = 0; in nhm_pci_cfg_setup()
51 reg.pci_size_low = PCIE_CONF_HDR_SIZE; /* overriden in pciex */ in nhm_pci_cfg_setup()
55 reg.pci_phys_hi = ((SOCKET_BUS(i)) in nhm_pci_cfg_setup()
61 (int *)&reg, sizeof (reg)/sizeof (int)) != in nhm_pci_cfg_setup()
108 nhm_pci_getb(int bus, int dev, int func, int reg, int *interpose) in nhm_pci_getb() argument
113 return (cmi_pci_getb(bus, dev, func, reg, interpose, hdl)); in nhm_pci_getb()
117 nhm_pci_getw(int bus, int dev, int func, int reg, int *interpose) in nhm_pci_getw() argument
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/titanic_41/usr/src/uts/common/io/mii/
H A Dmii_marvell.c151 uint16_t reg; in mvphy_reset_88e3016() local
156 reg = phy_read(ph, MVPHY_PSC); in mvphy_reset_88e3016()
158 reg |= MV_PSC_AUTO_MDIX; in mvphy_reset_88e3016()
159 reg &= ~(MV_PSC_EN_DETECT | MV_PSC_DIS_SCRAMBLER); in mvphy_reset_88e3016()
160 reg |= MV_PSC_LPNP; in mvphy_reset_88e3016()
165 phy_write(ph, MVPHY_PSC, reg); in mvphy_reset_88e3016()
184 uint16_t reg; in mvphy_loop_88e3016() local
193 reg = phy_read(ph, MII_CONTROL); in mvphy_loop_88e3016()
194 reg |= MII_CONTROL_RESET; in mvphy_loop_88e3016()
195 phy_write(ph, MII_CONTROL, reg); in mvphy_loop_88e3016()
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/titanic_41/usr/src/uts/common/io/i40e/
H A Di40e_intr.c213 uint32_t reg; in i40e_intr_adminq_enable() local
215 reg = I40E_PFINT_DYN_CTL0_INTENA_MASK | in i40e_intr_adminq_enable()
218 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, reg); in i40e_intr_adminq_enable()
226 uint32_t reg; in i40e_intr_adminq_disable() local
228 reg = I40E_ITR_INDEX_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT; in i40e_intr_adminq_disable()
229 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, reg); in i40e_intr_adminq_disable()
235 uint32_t reg; in i40e_intr_io_enable() local
238 reg = I40E_PFINT_DYN_CTLN_INTENA_MASK | in i40e_intr_io_enable()
241 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vector - 1), reg); in i40e_intr_io_enable()
247 uint32_t reg; in i40e_intr_io_disable() local
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/titanic_41/usr/src/uts/intel/io/intel_nb5000/
H A Dnb_pci_cfg.c49 pci_regspec_t reg; in nb_pci_cfg_setup() local
52 reg.pci_phys_hi = 16 << PCI_REG_DEV_SHIFT; /* Bus=0, Dev=16, Func=0 */ in nb_pci_cfg_setup()
53 reg.pci_phys_mid = 0; in nb_pci_cfg_setup()
54 reg.pci_phys_low = 0; in nb_pci_cfg_setup()
55 reg.pci_size_hi = 0; in nb_pci_cfg_setup()
56 reg.pci_size_low = PCIE_CONF_HDR_SIZE; /* overriden in pciex */ in nb_pci_cfg_setup()
60 (int *)&reg, sizeof (reg)/sizeof (int)) != DDI_PROP_SUCCESS) in nb_pci_cfg_setup()
67 reg.pci_phys_hi += 1 << PCI_REG_FUNC_SHIFT; in nb_pci_cfg_setup()
69 reg.pci_phys_hi = 17 << PCI_REG_DEV_SHIFT; /* Bus=0, Dev=17, Func=0 */ in nb_pci_cfg_setup()
72 (int *)&reg, sizeof (reg)/sizeof (int)) != DDI_PROP_SUCCESS) in nb_pci_cfg_setup()
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/titanic_41/usr/src/uts/i86pc/sys/
H A Dpci_cfgspace_impl.h41 extern uint8_t pci_mech1_getb(int bus, int dev, int func, int reg);
42 extern uint16_t pci_mech1_getw(int bus, int dev, int func, int reg);
43 extern uint32_t pci_mech1_getl(int bus, int dev, int func, int reg);
44 extern void pci_mech1_putb(int bus, int dev, int func, int reg, uint8_t val);
45 extern void pci_mech1_putw(int bus, int dev, int func, int reg, uint16_t val);
46 extern void pci_mech1_putl(int bus, int dev, int func, int reg, uint32_t val);
52 extern uint8_t pci_mech1_amd_getb(int bus, int dev, int func, int reg);
53 extern uint16_t pci_mech1_amd_getw(int bus, int dev, int func, int reg);
54 extern uint32_t pci_mech1_amd_getl(int bus, int dev, int func, int reg);
55 extern void pci_mech1_amd_putb(int bus, int dev, int func, int reg,
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/titanic_41/usr/src/uts/common/io/cxgbe/t4nex/
H A Dadapter.c26 t4_read_reg(struct adapter *sc, uint32_t reg) in t4_read_reg() argument
29 return (ddi_get32(sc->regh, (uint32_t *)(sc->regp + reg))); in t4_read_reg()
33 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) in t4_write_reg() argument
36 ddi_put32(sc->regh, (uint32_t *)(sc->regp + reg), val); in t4_write_reg()
40 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) in t4_os_pci_read_cfg1() argument
42 *val = pci_config_get8(sc->pci_regh, reg); in t4_os_pci_read_cfg1()
46 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) in t4_os_pci_write_cfg1() argument
48 pci_config_put8(sc->pci_regh, reg, val); in t4_os_pci_write_cfg1()
52 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) in t4_os_pci_read_cfg2() argument
54 *val = pci_config_get16(sc->pci_regh, reg); in t4_os_pci_read_cfg2()
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/titanic_41/usr/src/uts/common/io/audio/drv/audio1575/
H A Daudio1575.h395 #define GET8(reg) \ argument
396 ddi_get8(statep->regsh, (void *)(statep->regsp + (reg)))
398 #define GET16(reg) \ argument
399 ddi_get16(statep->regsh, (void *)(statep->regsp + (reg)))
401 #define GET32(reg) \ argument
402 ddi_get32(statep->regsh, (void *)(statep->regsp + (reg)))
404 #define PUT8(reg, val) \ argument
405 ddi_put8(statep->regsh, (void *)(statep->regsp + (reg)), (val))
407 #define PUT16(reg, val) \ argument
408 ddi_put16(statep->regsh, (void *)(statep->regsp + (reg)), (val))
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/titanic_41/usr/src/uts/common/sys/
H A Dvgasubr.h42 extern int vga_get_reg(struct vgaregmap *reg, int i);
43 extern void vga_set_reg(struct vgaregmap *reg, int i, int v);
44 extern int vga_get_crtc(struct vgaregmap *reg, int i);
45 extern void vga_set_crtc(struct vgaregmap *reg, int i, int v);
46 extern int vga_get_seq(struct vgaregmap *reg, int i);
47 extern void vga_set_seq(struct vgaregmap *reg, int i, int v);
48 extern int vga_get_grc(struct vgaregmap *reg, int i);
49 extern void vga_set_grc(struct vgaregmap *reg, int i, int v);
50 extern int vga_get_atr(struct vgaregmap *reg, int i);
51 extern void vga_set_atr(struct vgaregmap *reg, int i, int v);
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/titanic_41/usr/src/cmd/rcm_daemon/common/
H A Dmpxio_rcm.c163 phci_list_t *reg; in rcm_mod_fini() local
172 reg = reg_list; in rcm_mod_fini()
173 while (reg) { in rcm_mod_fini()
174 next = reg->next; in rcm_mod_fini()
175 free(reg->phci.path); in rcm_mod_fini()
176 free(reg); in rcm_mod_fini()
177 reg = next; in rcm_mod_fini()
245 phci_list_t *reg; in mpxio_unregister() local
251 for (reg = reg_list; reg != NULL; reg = reg->next) { in mpxio_unregister()
252 (void) rcm_unregister_interest(hdl, reg->phci.path, 0); in mpxio_unregister()
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/titanic_41/usr/src/uts/i86pc/os/
H A Dpci_mech1.c48 pci_mech1_getb(int bus, int device, int function, int reg) in pci_mech1_getb() argument
57 outl(PCI_CONFADD, PCI_CADDR1(bus, device, function, reg)); in pci_mech1_getb()
58 val = inb(PCI_CONFDATA | (reg & 0x3)); in pci_mech1_getb()
64 pci_mech1_getw(int bus, int device, int function, int reg) in pci_mech1_getw() argument
74 outl(PCI_CONFADD, PCI_CADDR1(bus, device, function, reg)); in pci_mech1_getw()
75 val = inw(PCI_CONFDATA | (reg & 0x2)); in pci_mech1_getw()
81 pci_mech1_getl(int bus, int device, int function, int reg) in pci_mech1_getl() argument
91 outl(PCI_CONFADD, PCI_CADDR1(bus, device, function, reg)); in pci_mech1_getl()
98 pci_mech1_putb(int bus, int device, int function, int reg, uint8_t val) in pci_mech1_putb() argument
106 outl(PCI_CONFADD, PCI_CADDR1(bus, device, function, reg)); in pci_mech1_putb()
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H A Dpci_mech1_amd.c95 pci_mech1_amd_getb(int bus, int device, int function, int reg) in pci_mech1_amd_getb() argument
105 outl(PCI_CONFADD, PCI_CADDR1_ECS(bus, device, function, reg)); in pci_mech1_amd_getb()
106 val = inb(PCI_CONFDATA | (reg & 0x3)); in pci_mech1_amd_getb()
112 pci_mech1_amd_getw(int bus, int device, int function, int reg) in pci_mech1_amd_getw() argument
122 outl(PCI_CONFADD, PCI_CADDR1_ECS(bus, device, function, reg)); in pci_mech1_amd_getw()
123 val = inw(PCI_CONFDATA | (reg & 0x2)); in pci_mech1_amd_getw()
129 pci_mech1_amd_getl(int bus, int device, int function, int reg) in pci_mech1_amd_getl() argument
139 outl(PCI_CONFADD, PCI_CADDR1_ECS(bus, device, function, reg)); in pci_mech1_amd_getl()
146 pci_mech1_amd_putb(int bus, int device, int function, int reg, uint8_t val) in pci_mech1_amd_putb() argument
154 outl(PCI_CONFADD, PCI_CADDR1_ECS(bus, device, function, reg)); in pci_mech1_amd_putb()
[all …]
/titanic_41/usr/src/cmd/fm/modules/common/fabric-xlate/
H A Dfx_fire.c139 uint64_t reg; in fab_xlate_fire_ce() local
155 if (nvlist_lookup_uint64(erpt, "tlu-cess", &reg) == 0) { in fab_xlate_fire_ce()
156 data->pcie_ce_status = (uint32_t)reg | (uint32_t)(reg >> 32); in fab_xlate_fire_ce()
167 uint64_t reg; in fab_xlate_fire_ue() local
195 if (nvlist_lookup_uint64(erpt, "tlu-uess", &reg) == 0) { in fab_xlate_fire_ue()
196 data->pcie_ue_status = (uint32_t)reg | (uint32_t)(reg >> 32); in fab_xlate_fire_ue()
200 if ((reg & (uint64_t)entry->fire_bit) && in fab_xlate_fire_ue()
211 if (nvlist_lookup_uint64(erpt, "tlu-tueh1l", &reg) == 0) { in fab_xlate_fire_ue()
212 data->pcie_ue_hdr[0] = (uint32_t)(reg >> 32); in fab_xlate_fire_ue()
213 data->pcie_ue_hdr[1] = (uint32_t)(reg); in fab_xlate_fire_ue()
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/titanic_41/usr/src/uts/common/io/e1000g/
H A De1000_osdep.h106 #define E1000_WRITE_REG(hw, reg, value) \ argument
110 (uint32_t *)((uintptr_t)(hw)->hw_addr + reg), \
115 e1000_translate_register_82542(reg)), \
119 #define E1000_READ_REG(hw, reg) (\ argument
122 (uint32_t *)((uintptr_t)(hw)->hw_addr + reg)) : \
125 e1000_translate_register_82542(reg))))
127 #define E1000_WRITE_REG_ARRAY(hw, reg, offset, value) \ argument
132 reg + ((offset) << 2)),\
137 e1000_translate_register_82542(reg) + \
141 #define E1000_READ_REG_ARRAY(hw, reg, offset) (\ argument
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/titanic_41/usr/src/lib/libc/sparcv9/gen/
H A Dmakectxt.c57 greg_t *reg; in makecontext() local
64 reg = ucp->uc_mcontext.gregs; in makecontext()
65 reg[REG_PC] = (greg_t)func; in makecontext()
66 reg[REG_nPC] = reg[REG_PC] + 0x4; in makecontext()
96 *tsp++ = reg[REG_O0 + argno] = va_arg(ap, long); in makecontext()
103 reg[REG_SP] = (greg_t)sp - STACK_BIAS; /* sp (when done) */ in makecontext()
104 reg[REG_O7] = (greg_t)resumecontext - 8; /* return pc */ in makecontext()
110 greg_t *reg; in __makecontext_v2() local
117 reg = ucp->uc_mcontext.gregs; in __makecontext_v2()
118 reg[REG_PC] = (greg_t)func; in __makecontext_v2()
[all …]
/titanic_41/usr/src/lib/libc/sparc/gen/
H A Dmakectxt.c57 greg_t *reg; in makecontext() local
64 reg = ucp->uc_mcontext.gregs; in makecontext()
65 reg[REG_PC] = (greg_t)func; in makecontext()
66 reg[REG_nPC] = reg[REG_PC] + 0x4; in makecontext()
96 *tsp++ = reg[REG_O0 + argno] = va_arg(ap, long); in makecontext()
103 reg[REG_SP] = (greg_t)sp - STACK_BIAS; /* sp (when done) */ in makecontext()
104 reg[REG_O7] = (greg_t)resumecontext - 8; /* return pc */ in makecontext()
110 greg_t *reg; in __makecontext_v2() local
117 reg = ucp->uc_mcontext.gregs; in __makecontext_v2()
118 reg[REG_PC] = (greg_t)func; in __makecontext_v2()
[all …]
/titanic_41/usr/src/lib/libdtrace/common/
H A Ddt_regset.c78 int reg; in dt_regset_assert_free() local
80 for (reg = 0; reg < drp->dr_size; reg++) { in dt_regset_assert_free()
81 if (BT_TEST(drp->dr_bitmap, reg) != 0) { in dt_regset_assert_free()
82 dt_dprintf("%%r%d was left allocated\n", reg); in dt_regset_assert_free()
110 int reg; in dt_regset_alloc() local
114 reg = (int)((wx << BT_ULSHIFT) | bx); in dt_regset_alloc()
115 BT_SET(drp->dr_bitmap, reg); in dt_regset_alloc()
116 return (reg); in dt_regset_alloc()
127 dt_regset_free(dt_regset_t *drp, int reg) in dt_regset_free() argument
129 assert(reg >= 0 && reg < drp->dr_size); in dt_regset_free()
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/titanic_41/usr/src/uts/common/io/igb/
H A De1000_osdep.h116 #define E1000_WRITE_REG(hw, reg, value) \ argument
118 (uint32_t *)((uintptr_t)(hw)->hw_addr + reg), (value))
120 #define E1000_READ_REG(hw, reg) \ argument
122 (uint32_t *)((uintptr_t)(hw)->hw_addr + reg))
124 #define E1000_WRITE_REG_ARRAY(hw, reg, offset, value) \ argument
126 (uint32_t *)((uintptr_t)(hw)->hw_addr + reg + ((offset) << 2)), \
129 #define E1000_READ_REG_ARRAY(hw, reg, offset) \ argument
131 (uint32_t *)((uintptr_t)(hw)->hw_addr + reg + ((offset) << 2)))
133 #define E1000_WRITE_REG_ARRAY_DWORD(a, reg, offset, value) \ argument
134 E1000_WRITE_REG_ARRAY(a, reg, offset, value)
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/titanic_41/usr/src/uts/intel/brand/common/
H A Dbrand_asm.h152 #define GET_V(sp, pcnt, var, reg) \ argument
153 mov V_OFFSET(pcnt, var)(sp), reg
155 #define SET_V(sp, pcnt, var, reg) \ argument
156 mov reg, V_OFFSET(pcnt, var)(sp)
158 #define GET_PROCP(sp, pcnt, reg) \ argument
159 GET_V(sp, pcnt, V_LWP, reg); /* get lwp pointer */ \
160 mov LWP_PROCP(reg), reg /* get proc pointer */
162 #define GET_P_BRAND_DATA(sp, pcnt, reg) \ argument
163 GET_PROCP(sp, pcnt, reg); \
164 mov P_BRAND_DATA(reg), reg /* get p_brand_data */
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/titanic_41/usr/src/uts/sun/sys/
H A Dzsdev.h95 #define SCC_WRITEA(reg, val) { \ argument
97 ((uintptr_t)zs->zs_addr | ZSOFF))->zscc_control = reg; \
102 zs->zs_wreg[reg] = val; \
104 #define SCC_WRITEB(reg, val) { \ argument
106 ((uintptr_t)zs->zs_addr & ~ZSOFF))->zscc_control = reg; \
111 zs->zs_wreg[reg] = val; \
113 #define SCC_WRITE(reg, val) { \ argument
114 zs->zs_addr->zscc_control = reg; \
118 zs->zs_wreg[reg] = val; \
121 #define SCC_READA(reg, var) { \ argument
[all …]
/titanic_41/usr/src/uts/common/io/ntxn/
H A Dniu.c99 unm_niu_gbe_phy_read(struct unm_adapter_s *adapter, long reg, in unm_niu_gbe_phy_read() argument
134 address.reg_addr = (unm_crbword_t)reg; in unm_niu_gbe_phy_read()
405 unm_niu_gb_drop_crc_t reg; in unm_niu_set_promiscuous_mode() local
446 &reg, 4); in unm_niu_set_promiscuous_mode()
449 reg.drop_gb0 = data; in unm_niu_set_promiscuous_mode()
452 reg.drop_gb1 = data; in unm_niu_set_promiscuous_mode()
455 reg.drop_gb2 = data; in unm_niu_set_promiscuous_mode()
458 reg.drop_gb3 = data; in unm_niu_set_promiscuous_mode()
465 &reg, 4); in unm_niu_set_promiscuous_mode()
552 long reg; in unm_niu_xg_set_promiscuous_mode() local
[all …]
/titanic_41/usr/src/uts/common/io/pciex/hotplug/
H A Dpcishpc.c100 static uint32_t pcishpc_read_reg(pcie_hp_ctrl_t *ctrl_p, int reg);
101 static void pcishpc_write_reg(pcie_hp_ctrl_t *ctrl_p, int reg,
261 uint32_t irq_locator, irq_serr_locator, reg; in pcishpc_intr() local
280 reg = pcishpc_read_reg(ctrl_p, PCI_HP_CTRL_SERR_INT_REG); in pcishpc_intr()
282 if (reg & PCI_HP_SERR_INT_CMD_COMPLETE_IRQ) { in pcishpc_intr()
289 if (reg & PCI_HP_SERR_INT_ARBITER_IRQ) { in pcishpc_intr()
296 pcishpc_write_reg(ctrl_p, PCI_HP_CTRL_SERR_INT_REG, reg); in pcishpc_intr()
309 reg = pcishpc_read_reg(ctrl_p, in pcishpc_intr()
312 if (reg & PCI_HP_SLOT_PRESENCE_DETECTED) in pcishpc_intr()
317 if (reg & PCI_HP_SLOT_ISO_PWR_DETECTED) in pcishpc_intr()
[all …]
/titanic_41/usr/src/uts/common/io/atge/
H A Datge_mii.c64 atge_mii_read(void *arg, uint8_t phy, uint8_t reg) in atge_mii_read() argument
73 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); in atge_mii_read()
86 phy, reg); in atge_mii_read()
97 if (reg == MII_STATUS) in atge_mii_read()
99 else if (reg == MII_EXTSTATUS) in atge_mii_read()
107 atge_mii_write(void *arg, uint8_t phy, uint8_t reg, uint16_t val) in atge_mii_write() argument
117 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); in atge_mii_write()
130 " val :%d", phy, reg, val); in atge_mii_write()
187 uint16_t reg, pn; in atge_l1_mii_reset() local
207 reg = atge_mii_read(atgep, phyaddr, ATPHY_CDTC); in atge_l1_mii_reset()
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12345678910>>...25