| /titanic_41/usr/src/cmd/mdb/intel/amd64/kmdb/ |
| H A D | kmdb_asmutil.s | 69 rdmsr(uint32_t addr, uint64_t *retp)
74 ENTRY(rdmsr)
76 rdmsr
80 SET_SIZE(rdmsr)
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| /titanic_41/usr/src/cmd/mdb/intel/ia32/kmdb/ |
| H A D | kmdb_asmutil.s | 73 rdmsr(uint32_t addr, uint64_t *retp)
78 ENTRY(rdmsr)
80 rdmsr
85 SET_SIZE(rdmsr)
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| /titanic_41/usr/src/uts/i86pc/os/cpupm/ |
| H A D | turbo.c | 109 mcnt = rdmsr(IA32_MPERF_MSR); in update_turbo_info()
110 acnt = rdmsr(IA32_APERF_MSR); in update_turbo_info()
128 mcnt = rdmsr(IA32_MPERF_MSR); in get_turbo_info()
129 acnt = rdmsr(IA32_APERF_MSR); in get_turbo_info()
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| H A D | cpupm_throttle.c | 95 reg = rdmsr(IA32_CLOCK_MODULATION_MSR); in write_ctrl()
130 reg = rdmsr(IA32_CLOCK_MODULATION_MSR); in read_status()
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| H A D | speedstep.c | 106 reg = rdmsr(IA32_PERF_CTL_MSR); in write_ctrl()
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| /titanic_41/usr/src/uts/i86pc/io/pcplusmp/ |
| H A D | apic_regops.c | 157 i = (uint64_t)(rdmsr(REG_X2APIC_BASE_MSR + (msr >> 2)) & 0xffffffff); in local_x2apic_read()
167 tmp = rdmsr(REG_X2APIC_BASE_MSR + (msr >> 2)); in local_x2apic_write()
179 return (rdmsr(REG_X2APIC_BASE_MSR + (APIC_TASK_REG >> 2))); in get_local_x2apic_pri()
259 apic_base_msr = rdmsr(REG_APIC_BASE_MSR); in apic_enable_x2apic()
278 apic_base_msr = rdmsr(REG_APIC_BASE_MSR); in apic_local_mode()
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| H A D | apic_timer.c | 312 ticks = rdmsr(IA32_DEADLINE_TSC_MSR); in deadline_timer_enable()
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| /titanic_41/usr/src/uts/intel/pcbe/ |
| H A D | p123_pcbe.c | 708 pes[0] = rdmsr(REG_PERFEVNT0); in ptm_pcbe_overflow_bitmap()
718 pes[1] = rdmsr(REG_PERFEVNT1); in ptm_pcbe_overflow_bitmap()
933 pic0->ptm_rawpic = rdmsr(P5_CTR0); in ptm_pcbe_program()
934 pic1->ptm_rawpic = rdmsr(P5_CTR1); in ptm_pcbe_program()
994 curpic[0] = rdmsr(P5_CTR0); in ptm_pcbe_sample()
995 curpic[1] = rdmsr(P5_CTR1); in ptm_pcbe_sample()
997 curpic[0] = rdmsr(REG_PERFCTR0); in ptm_pcbe_sample()
998 curpic[1] = rdmsr(REG_PERFCTR1); in ptm_pcbe_sample()
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| H A D | p4_pcbe.c | 608 if (rdmsr(p4_ctrs[i].pc_ctladdr) & CCCR_OVF) in p4_pcbe_overflow_bitmap()
1010 curpic[i] = rdmsr(p4_ctrs[i].pc_caddr); in p4_pcbe_sample()
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| H A D | opteron_pcbe.c | 794 curpic[i] = rdmsr(PIC_BASE_ADDR + i); in opt_pcbe_sample()
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| /titanic_41/usr/src/uts/i86pc/ml/ |
| H A D | bios_call_src.s | 135 rdmsr
143 rdmsr
151 rdmsr
238 rdmsr
359 rdmsr
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| H A D | mpcore.s | 168 rdmsr
320 rdmsr
422 rdmsr
513 rdmsr
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| H A D | cpr_wakecode.s | 141 rdmsr
150 rdmsr
155 rdmsr
379 rdmsr
668 rdmsr
1086 rdmsr
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| H A D | fb_swtch_src.s | 245 rdmsr
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| /titanic_41/usr/src/uts/i86pc/dboot/ |
| H A D | dboot_grub.s | 149 rdmsr
166 rdmsr
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| /titanic_41/usr/src/cmd/mdb/intel/kmdb/ |
| H A D | kmdb_asmutil.h | 41 extern void rdmsr(uint32_t, uint64_t *);
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| H A D | kvm_isadep.c | 330 if (kmt_rwmsr(addr, &val, rdmsr) < 0) { in kmt_rdmsr()
365 if (kmt_rwmsr(msr->msr_num, &val, rdmsr) < 0) in kmt_msr_validate()
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| /titanic_41/usr/src/uts/i86pc/os/ |
| H A D | mp_startup.c | 771 if (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) || in do_erratum_298()
772 ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0)) { in do_erratum_298()
783 (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) || in do_erratum_298()
784 ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0))) { in do_erratum_298()
1212 rdmsr(MSR_AMD_DE_CFG) | AMD_DE_CFG_E721); in workaround_errata()
2065 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) | in cpu_asysc_enable()
2079 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) & in cpu_asysc_disable()
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| H A D | mach_kdi.c | 166 old = (uintptr_t)rdmsr(MSR_AMD_GSBASE); in boot_kdi_tmpinit()
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| H A D | pci_mech1_amd.c | 75 wrmsr(MSR_AMD_NB_CFG, rdmsr(MSR_AMD_NB_CFG) | AMD_GH_NB_CFG_EN_ECS); in pci_check_amd_ioecs()
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| H A D | microcode.c | 887 uinfop->cui_rev = rdmsr(MSR_AMD_PATCHLEVEL); in ucode_read_rev_amd()
902 uinfop->cui_rev = (rdmsr(MSR_INTC_UCODE_REV) >> INTC_UCODE_REV_SHIFT); in ucode_read_rev_intel()
1187 uinfop->cui_platid = 1 << ((rdmsr(MSR_INTC_PLATFORM_ID) >> in ucode_check()
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| /titanic_41/usr/src/uts/intel/amd64/sys/ |
| H A D | privregs.h | 133 rdmsr; \
137 rdmsr; \
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| /titanic_41/usr/src/grub/grub-0.97/netboot/ |
| H A D | cpu.h | 193 #define rdmsr(msr,val1,val2) \ macro
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| /titanic_41/usr/src/uts/intel/kdi/amd64/ |
| H A D | kdi_asm.s | 90 rdmsr; \
559 rdmsr /* addr in %ecx, value into %edx:%eax */
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| /titanic_41/usr/src/uts/intel/ia32/ml/ |
| H A D | i86_subr.s | 2878 rdmsr(uint_t r)
2916 ENTRY(rdmsr)
2918 rdmsr
2922 SET_SIZE(rdmsr)
2938 rdmsr
2979 ENTRY(rdmsr)
2981 rdmsr
2983 SET_SIZE(rdmsr)
2999 rdmsr
3086 rdmsr; \
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