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Searched refs:r_tstate (Results 1 – 25 of 27) sorted by relevance

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/titanic_41/usr/src/uts/sparc/v9/os/
H A Dsimulator.c93 ASSERT(USERMODE(rp->r_tstate)); in do_unaligned()
175 asi = (uint_t)(rp->r_tstate >> TSTATE_ASI_SHIFT) & in do_unaligned()
573 usermode = USERMODE(rp->r_tstate); in simulate_lddstd()
586 if (USERMODE(rp->r_tstate)) in simulate_lddstd()
593 asi = (uint_t)(rp->r_tstate >> TSTATE_ASI_SHIFT) & in simulate_lddstd()
797 s1 = ((rp->r_tstate & TSTATE_IN) >> (TSTATE_CCR_SHIFT + 3)) ^ in simulate_mulscc()
798 ((rp->r_tstate & TSTATE_IV) >> (TSTATE_CCR_SHIFT + 1)); in simulate_mulscc()
813 rp->r_tstate &= ~TSTATE_ICC; in simulate_mulscc()
814 rp->r_tstate |= (uint64_t)((c >> 31) & 1) << (TSTATE_CCR_SHIFT + 0); in simulate_mulscc()
815 rp->r_tstate |= (uint64_t)((v >> 31) & 1) << (TSTATE_CCR_SHIFT + 1); in simulate_mulscc()
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H A Dv9dep.c340 rp->r_tstate &= ~(((uint64_t)TSTATE_CCR_MASK << TSTATE_CCR_SHIFT) | in setgregs()
342 rp->r_tstate |= tbits; in setgregs()
404 grp[REG_CCR] = (rp->r_tstate >> TSTATE_CCR_SHIFT) & TSTATE_CCR_MASK; in getgregs()
423 grp[REG_ASI] = (rp->r_tstate >> TSTATE_ASI_SHIFT) & TSTATE_ASI_MASK; in getgregs()
441 grp[REG_PSR] = mkpsr(rp->r_tstate, fprs); in getgregs32()
810 rp->r_tstate = TSTATE_USER32 | weakest_mem_model; in setregs()
812 rp->r_tstate = TSTATE_USER64 | weakest_mem_model; in setregs()
814 rp->r_tstate &= ~TSTATE_PEF; in setregs()
1165 rp->r_tstate &= ~((uint64_t)TSTATE_ASI_MASK << TSTATE_ASI_SHIFT); in sendsig()
1166 rp->r_tstate |= ((uint64_t)ASI_PNF << TSTATE_ASI_SHIFT); in sendsig()
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H A Dxregs.c178 xregs->pr_un.pr_v8p.pr_tstate = rp->r_tstate; in xregs_getgregs()
298 rp->r_tstate &= ~((uint64_t)CCR_XCC << TSTATE_CCR_SHIFT); in xregs_setgregs()
299 rp->r_tstate |= xregs->pr_un.pr_v8p.pr_tstate & in xregs_setgregs()
301 rp->r_tstate &= ~((uint64_t)TSTATE_ASI_MASK << TSTATE_ASI_SHIFT); in xregs_setgregs()
302 rp->r_tstate |= xregs->pr_un.pr_v8p.pr_tstate & in xregs_setgregs()
/titanic_41/usr/src/uts/sparc/v9/fpu/
H A Dfpu.c226 if (USERMODE(rp->r_tstate)) { in fp_disabled()
440 if (USERMODE(rp->r_tstate)) { in fp_precise()
515 if (USERMODE(rp->r_tstate)) { in fp_precise()
H A Duword.c210 } else if (USERMODE(pregs->r_tstate)) { /* locals and ins */ in read_iureg()
270 } else if (USERMODE(pregs->r_tstate)) { /* locals and ins */ in write_iureg()
H A Dv9instr.c67 asi = (uint32_t)((pregs->r_tstate >> TSTATE_ASI_SHIFT) & in fldst()
284 tstate = pregs->r_tstate; in fmovcc_icc()
/titanic_41/usr/src/uts/sun4v/cpu/
H A Dgeneric.c235 if (!USERMODE(rp->r_tstate)) in vis1_partial_support()
244 asi = (uint32_t)((rp->r_tstate >> TSTATE_ASI_SHIFT) & in vis1_partial_support()
H A Dniagara.c276 if (!USERMODE(rp->r_tstate)) in vis1_partial_support()
285 asi = (uint32_t)((rp->r_tstate >> TSTATE_ASI_SHIFT) & in vis1_partial_support()
/titanic_41/usr/src/uts/sparc/fs/proc/
H A Dprmachdep.c209 lwptoregs(lwp)->r_tstate = TSTATE_USER64|TSTATE_MM_TSO; in prsetprregs()
211 lwptoregs(lwp)->r_tstate = TSTATE_USER32|TSTATE_MM_TSO; in prsetprregs()
213 lwptoregs(lwp)->r_tstate &= ~TSTATE_PEF; in prsetprregs()
293 dest[R_CCR] = ((r->r_tstate >> TSTATE_CCR_SHIFT) & CCR_XCC) | in prgregset_32ton()
300 dest[R_ASI] = (r->r_tstate >> TSTATE_ASI_SHIFT) & TSTATE_ASI_MASK; in prgregset_32ton()
380 if (r->r_tstate & TSTATE_IC) in prgetrvals()
/titanic_41/usr/src/uts/sun4v/os/
H A Dmach_trap.c140 rp->r_tstate, sfmmu_getctx_sec()); in showregs()
141 if (USERMODE(rp->r_tstate)) { in showregs()
/titanic_41/usr/src/uts/sun4u/os/
H A Dmach_trap.c155 rp->r_tstate, sfmmu_getctx_sec()); in showregs()
156 if (USERMODE(rp->r_tstate)) { in showregs()
/titanic_41/usr/src/uts/sun4/os/
H A Dtrap.c178 if (USERMODE(rp->r_tstate) || (type & T_USER)) { in trap()
1377 if (USERMODE(rp->r_tstate)) { in fpu_trap()
1622 if (USERMODE(rp->r_tstate)) in nfload()
1636 asi = (uint_t)((rp->r_tstate >> TSTATE_ASI_SHIFT) & in nfload()
1642 as = USERMODE(rp->r_tstate) ? ttoproc(curthread)->p_as : &kas; in nfload()
1907 if (USERMODE(rp->r_tstate)) in get_accesstype()
H A Dvisinstr.c95 ASSERT(USERMODE(pregs->r_tstate)); in vis_fpu_simulator()
397 if ((pregs->r_tstate & TSTATE_AM) != 0) { in vis_edge()
534 pregs->r_tstate &= ~((uint64_t)TSTATE_CCR_MASK in vis_edge()
537 pregs->r_tstate |= ((uint64_t)ccr << TSTATE_CCR_SHIFT); in vis_edge()
1382 ASSERT(USERMODE(pregs->r_tstate)); in vis_fldst()
/titanic_41/usr/src/uts/sparc/dtrace/
H A Ddtrace_isa.c762 return ((rp->r_tstate >> TSTATE_CCR_SHIFT) & in dtrace_getreg()
771 return ((rp->r_tstate >> TSTATE_ASI_SHIFT) & in dtrace_getreg()
H A Dfasttrap_isa.c675 uint_t ccr = rp->r_tstate >> TSTATE_CCR_SHIFT; in fasttrap_pid_probe()
/titanic_41/usr/src/uts/sparc/v9/sys/
H A Dprivregs.h48 long long r_tstate; member
72 #define r_ps r_tstate
/titanic_41/usr/src/uts/sparc/os/
H A Dsyscall.c609 rp->r_tstate &= ~TSTATE_IC; in post_syscall()
632 rp->r_tstate |= TSTATE_IC; in post_syscall()
/titanic_41/usr/src/uts/sparc/v9/ml/
H A Dsparcv9_subr.s1730 ! The v9 struct regs has a 64-bit r_tstate field, which we use here
/titanic_41/usr/src/uts/sun4/ml/
H A Doffsets.in306 r_tstate TSTATE_OFF
/titanic_41/usr/src/cmd/mdb/sparc/kmdb/
H A Dkaif.c904 regs.r_tstate = kaif_cb_save.krs_tstate; in kaif_kernpanic()
/titanic_41/usr/src/uts/sun4u/cpu/
H A Dopl_olympus.c1945 aflt->flt_priv = (uchar_t)(tl == 1 ? 1 : ((rp->r_tstate &
2125 aflt->flt_priv = (uchar_t)(tl == 1 ? 1 : ((rp->r_tstate & TSTATE_PRIV) ?
H A Dus3_cheetahplus.c1024 aflt->flt_priv = (rp->r_tstate & TSTATE_PRIV) ? 1 : 0; in cpu_tlb_parity_error()
H A Dus3_common.c1330 (rp->r_tstate & TSTATE_PRIV) ? 1 : 0, 0, ceen, nceen, clop); in cpu_fast_ecc_error()
1681 aflt->flt_priv = (rp->r_tstate & TSTATE_PRIV) ? 1 : 0; in cpu_disrupting_error()
1821 aflt->flt_priv = (rp->r_tstate & TSTATE_PRIV) ? 1 : 0; in cpu_deferred_error()
2114 aflt->flt_priv = (tl || (rp->r_tstate & TSTATE_PRIV)) ? 1 : 0; in cpu_parity_error()
/titanic_41/usr/src/uts/sun4v/ml/
H A Dmach_locore.s60 ! REGOFF must add up to allow double word access to r_tstate.
/titanic_41/usr/src/uts/sun4u/ml/
H A Dmach_locore.s60 ! REGOFF must add up to allow double word access to r_tstate.

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