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Searched refs:qlge (Results 1 – 16 of 16) sorted by relevance

/titanic_41/usr/src/uts/common/io/fibre-channel/fca/qlge/
H A Dqlge_flash.c41 ql_flash_id(qlge_t *qlge) in ql_flash_id() argument
50 rval = ql_read_flash(qlge, FLASH_CONF_ADDR | 0x300 | FLASH_RES_CMD, in ql_flash_id()
53 __func__, qlge->instance, fdata)); in ql_flash_id()
57 rval = ql_read_flash(qlge, FLASH_CONF_ADDR | 0x0400 | FLASH_RDID_CMD, in ql_flash_id()
62 __func__, qlge->instance, fdata); in ql_flash_id()
64 qlge->flash_info.flash_manuf = LSB(LSW(fdata)); in ql_flash_id()
65 qlge->flash_info.flash_id = MSB(LSW(fdata)); in ql_flash_id()
66 qlge->flash_info.flash_cap = LSB(MSW(fdata)); in ql_flash_id()
69 __func__, qlge->instance, in ql_flash_id()
70 qlge->flash_info.flash_manuf, qlge->flash_info.flash_id, in ql_flash_id()
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H A Dqlge_mpi.c35 ql_poll_processor_intr(qlge_t *qlge, uint8_t timeout) in ql_poll_processor_intr() argument
39 if (ql_wait_reg_bit(qlge, REG_STATUS, STS_PI, BIT_SET, timeout) in ql_poll_processor_intr()
51 ql_wait_processor_addr_reg_ready(qlge_t *qlge) in ql_wait_processor_addr_reg_ready() argument
55 if (ql_wait_reg_bit(qlge, REG_PROCESSOR_ADDR, in ql_wait_processor_addr_reg_ready()
69 ql_write_processor_data(qlge_t *qlge, uint32_t addr, uint32_t data) in ql_write_processor_data() argument
74 if (ql_wait_processor_addr_reg_ready(qlge) == DDI_FAILURE) in ql_write_processor_data()
77 ql_write_reg(qlge, REG_PROCESSOR_DATA, data); in ql_write_processor_data()
79 ql_write_reg(qlge, REG_PROCESSOR_ADDR, addr); in ql_write_processor_data()
81 if (ql_wait_processor_addr_reg_ready(qlge) == DDI_FAILURE) in ql_write_processor_data()
95 ql_read_processor_data(qlge_t *qlge, uint32_t addr, uint32_t *data) in ql_read_processor_data() argument
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H A Dqlge_gld.c86 qlge_t *qlge = (qlge_t *)arg; in ql_m_start() local
92 mutex_enter(&qlge->gen_mutex); in ql_m_start()
93 if (qlge->mac_flags == QL_MAC_SUSPENDED) { in ql_m_start()
94 mutex_exit(&qlge->gen_mutex); in ql_m_start()
97 mutex_enter(&qlge->hw_mutex); in ql_m_start()
98 qlge->mac_flags = QL_MAC_INIT; in ql_m_start()
103 (void) ql_unicst_set(qlge, in ql_m_start()
104 (uint8_t *)qlge->unicst_addr[0].addr.ether_addr_octet, 0); in ql_m_start()
105 qlge->stats.rpackets = 0; in ql_m_start()
106 qlge->stats.rbytes = 0; in ql_m_start()
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H A Dqlge.c67 static void ql_stop_timer(qlge_t *qlge);
68 static void ql_fm_fini(qlge_t *qlge);
169 ql_read_sh_reg(qlge_t *qlge, struct rx_ring *rx_ring) in ql_read_sh_reg() argument
174 (void) ddi_dma_sync(qlge->host_copy_shadow_dma_attr.dma_handle, in ql_read_sh_reg()
178 rtn = ddi_get32(qlge->host_copy_shadow_dma_attr.acc_handle, in ql_read_sh_reg()
212 ql_pci_config(qlge_t *qlge) in ql_pci_config() argument
216 qlge->vendor_id = (uint16_t)pci_config_get16(qlge->pci_handle, in ql_pci_config()
218 qlge->device_id = (uint16_t)pci_config_get16(qlge->pci_handle, in ql_pci_config()
231 w = (uint16_t)pci_config_get16(qlge->pci_handle, PCI_CONF_COMM); in ql_pci_config()
237 pci_config_put16(qlge->pci_handle, PCI_CONF_COMM, w); in ql_pci_config()
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H A Dqlge_dbg.c44 ql_get8(qlge_t *qlge, uint32_t index) in ql_get8() argument
48 ret = (uint8_t)ddi_get8(qlge->dev_handle, in ql_get8()
49 (uint8_t *)(((caddr_t)qlge->iobase) + index)); in ql_get8()
57 ql_get16(qlge_t *qlge, uint32_t index) in ql_get16() argument
61 ret = (uint16_t)ddi_get16(qlge->dev_handle, in ql_get16()
62 (uint16_t *)(void *)(((caddr_t)qlge->iobase) + index)); in ql_get16()
70 ql_get32(qlge_t *qlge, uint32_t index) in ql_get32() argument
74 ret = ddi_get32(qlge->dev_handle, in ql_get32()
75 (uint32_t *)(void *)(((caddr_t)qlge->iobase) + index)); in ql_get32()
83 ql_put8(qlge_t *qlge, uint32_t index, uint8_t data) in ql_put8() argument
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H A Dqlge_fm.c31 ql_fm_ereport(qlge_t *qlge, char *detail) in ql_fm_ereport() argument
38 if (DDI_FM_EREPORT_CAP(qlge->fm_capabilities)) { in ql_fm_ereport()
39 ddi_fm_ereport_post(qlge->dip, buf, ena, DDI_NOSLEEP, in ql_fm_ereport()
/titanic_41/usr/src/uts/common/sys/fibre-channel/fca/qlge/
H A Dqlge_dbg.h51 #define QLA_CORE_DUMP(qlge) ql_core_dump(qlge); argument
52 #define QLA_DUMP_CRASH_RECORD(qlge) ql_dump_crash_record(qlge) argument
54 #define QLA_CORE_DUMP(qlge)
55 #define QLA_DUMP_CRASH_RECORD(qlge)
66 if (qlge->ql_dbgprnt & dbg_level) ql_printf x
68 if (qlge->ql_dbgprnt & dbg_level) QL_DUMP_BUFFER(a, b, c, d)
70 #define QL_DUMP_REQ_PKT(qlge, pkt, oal, num) if (qlge->ql_dbgprnt & DBG_TX) \ argument
71 ql_dump_req_pkt(qlge, pkt, oal, num)
73 #define QL_DUMP_CQICB(qlge, cqicb) if (qlge->ql_dbgprnt & DBG_INIT) \ argument
74 ql_dump_cqicb(qlge, cqicb)
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H A Dqlge.h133 #define CARRIER_ON(qlge) mac_link_update((qlge)->mh, LINK_STATE_UP) argument
134 #define CARRIER_OFF(qlge) mac_link_update((qlge)->mh, LINK_STATE_DOWN) argument
190 #define RESUME_TX(tx_ring) mac_tx_update(tx_ring->qlge->mh);
191 #define RX_UPSTREAM(rx_ring, mp) mac_rx(rx_ring->qlge->mh, \
192 rx_ring->qlge->handle, mp);
445 struct qlge *qlge; member
511 struct qlge *qlge; member
581 struct qlge *qlge; member
606 typedef struct qlge { struct
645 #define CFG_IST(qlge, cfgflags) (qlge->cfg_flags & cfgflags) argument
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H A Dqlge_hw.h39 #define QLA_SCHULTZ(qlge) ((qlge)->device_id == ISP_SCHULTZ) argument
1124 #define ISP_ENABLE_INTR(qlge) ql_put32(qlge, \ argument
1127 #define ISP_DISABLE_INTR(qlge) ql_put32(qlge, \ argument
1130 #define ISP_ENABLE_PI_INTR(qlge) ql_put32(qlge, \ argument
1132 #define ISP_DISABLE_PI_INTR(qlge) ql_put32(qlge, \ argument
1135 #define ISP_ENABLE_GLOBAL_INTRS(qlge) { \ argument
1136 ql_put32(qlge, REG_INTERRUPT_ENABLE, \
1138 qlge->flags |= INTERRUPTS_ENABLED; \
1140 #define ISP_DISABLE_GLOBAL_INTRS(qlge) { \ argument
1141 ql_put32(qlge, \
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/titanic_41/usr/src/uts/intel/qlge/
H A DMakefile38 MODULE = qlge
60 INC_PATH += -I$(UTSBASE)/common/sys/fibre-channel/fca/qlge
/titanic_41/usr/src/uts/sparc/qlge/
H A DMakefile38 MODULE = qlge
60 INC_PATH += -I$(UTSBASE)/common/sys/fibre-channel/fca/qlge
/titanic_41/usr/src/pkg/manifests/
H A Ddriver-network-qlc.mf60 driver name=qlge alias=pciex1077,8000 perms="* 0666 root sys"
62 file path=kernel/drv/$(ARCH64)/qlge group=sys
66 $(i386_ONLY)file path=kernel/drv/qlge group=sys
/titanic_41/usr/src/uts/sparc/
H A DMakefile.sparc300 DRV_KMODS += qlge
/titanic_41/usr/src/uts/intel/
H A DMakefile.intel307 DRV_KMODS += qlge
/titanic_41/usr/src/uts/common/
H A DMakefile.rules1129 $(OBJS_DIR)/%.o: $(UTSBASE)/common/io/fibre-channel/fca/qlge/%.c
2409 $(LINTS_DIR)/%.ln: $(UTSBASE)/common/io/fibre-channel/fca/qlge/%.c
H A DMakefile.files1063 QLGE_OBJS += qlge.o qlge_dbg.o qlge_flash.o qlge_fm.o qlge_gld.o qlge_mpi.o