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Searched refs:pxu_p (Results 1 – 5 of 5) sorted by relevance

/titanic_41/usr/src/uts/sun4u/io/px/
H A Dpx_hlib.c169 static uint64_t msiq_suspend(devhandle_t dev_hdl, pxu_t *pxu_p);
170 static void msiq_resume(devhandle_t dev_hdl, pxu_t *pxu_p);
171 static void jbc_init(caddr_t xbc_csr_base, pxu_t *pxu_p);
172 static void ubc_init(caddr_t xbc_csr_base, pxu_t *pxu_p);
182 hvio_cb_init(caddr_t xbc_csr_base, pxu_t *pxu_p) in hvio_cb_init() argument
184 switch (PX_CHIP_TYPE(pxu_p)) { in hvio_cb_init()
186 ubc_init(xbc_csr_base, pxu_p); in hvio_cb_init()
189 jbc_init(xbc_csr_base, pxu_p); in hvio_cb_init()
193 PX_CHIP_TYPE(pxu_p)); in hvio_cb_init()
203 jbc_init(caddr_t xbc_csr_base, pxu_t *pxu_p) in jbc_init() argument
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H A Dpx_lib4u.c106 px_lib_map_regs(pxu_t *pxu_p, dev_info_t *dip) in px_lib_map_regs() argument
112 pxu_p, dip); in px_lib_map_regs()
121 if (ddi_regs_map_setup(dip, reg_bank, &pxu_p->px_address[reg_bank], in px_lib_map_regs()
122 0, 0, &attr, &pxu_p->px_ac[reg_bank]) != DDI_SUCCESS) { in px_lib_map_regs()
131 if (ddi_regs_map_setup(dip, reg_bank, &pxu_p->px_address[reg_bank], in px_lib_map_regs()
132 0, 0, &attr, &pxu_p->px_ac[reg_bank]) != DDI_SUCCESS) { in px_lib_map_regs()
136 pxu_p->px_address[reg_bank] -= FIRE_CONTROL_STATUS; in px_lib_map_regs()
141 reg_bank, pxu_p->px_address[reg_bank]); in px_lib_map_regs()
151 pxu_p->px_address[reg_bank] = NULL; in px_lib_map_regs()
152 ddi_regs_map_free(&pxu_p->px_ac[reg_bank]); in px_lib_map_regs()
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H A Dpx_lib4u.h78 #define PX_CHIP_TYPE(pxu_p) ((pxu_p)->chip_type) argument
300 extern void hvio_cb_init(caddr_t xbc_csr_base, pxu_t *pxu_p);
301 extern void hvio_ib_init(caddr_t csr_base, pxu_t *pxu_p);
302 extern void hvio_mmu_init(caddr_t csr_base, pxu_t *pxu_p);
303 extern void hvio_pec_init(caddr_t csr_base, pxu_t *pxu_p);
305 extern uint64_t hvio_intr_devino_to_sysino(devhandle_t dev_hdl, pxu_t *pxu_p,
315 extern uint64_t hvio_intr_gettarget(devhandle_t dev_hdl, pxu_t *pxu_p,
317 extern uint64_t hvio_intr_settarget(devhandle_t dev_hdl, pxu_t *pxu_p,
320 extern uint64_t hvio_iommu_map(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid,
323 extern uint64_t hvio_iommu_demap(devhandle_t dev_hdl, pxu_t *pxu_p,
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H A Dpx_tools_4u.c98 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; in pxtool_safe_phys_peek() local
106 pxu_p->pcitool_addr = (caddr_t)(paddr & px_paddr_mask); in pxtool_safe_phys_peek()
134 pxu_p->pcitool_addr = NULL; in pxtool_safe_phys_peek()
172 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; in pxtool_safe_phys_poke() local
197 pxu_p->pcitool_addr = (caddr_t)(paddr & px_paddr_mask); in pxtool_safe_phys_poke()
231 pxu_p->pcitool_addr = NULL; in pxtool_safe_phys_poke()
H A Dpx_err.c865 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; in px_err_snapshot() local
866 caddr_t xbc_csr_base = (caddr_t)pxu_p->px_address[PX_REG_XBC]; in px_err_snapshot()
867 caddr_t pec_csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; in px_err_snapshot()
869 uint8_t chip_mask = 1 << PX_CHIP_TYPE(pxu_p); in px_err_snapshot()
909 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; in px_err_erpt_and_clr() local
933 if (!(BIT_TST(err_reg_tbl->chip_mask, PX_CHIP_TYPE(pxu_p)))) in px_err_erpt_and_clr()
937 csr_base = (caddr_t)pxu_p->px_address[err_reg_tbl->reg_bank]; in px_err_erpt_and_clr()
1519 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; in px_jbc_pcitool_addr_match() local
1520 caddr_t pcitool_addr = pxu_p->pcitool_addr; in px_jbc_pcitool_addr_match()
1649 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; in px_err_imu_eq_ovfl_handle() local
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