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Searched refs:pl_intr (Results 1 – 7 of 7) sorted by relevance

/titanic_41/usr/src/uts/common/io/chxge/com/
H A Dulp.c47 u32 pl_intr = t1_read_reg_4(ulp->adapter, A_PL_ENABLE); in t1_ulp_intr_enable() local
51 pl_intr | F_PL_INTR_ULP); in t1_ulp_intr_enable()
66 u32 pl_intr = t1_read_reg_4(ulp->adapter, A_PL_ENABLE); in t1_ulp_intr_disable() local
69 pl_intr & ~F_PL_INTR_ULP); in t1_ulp_intr_disable()
H A Dmc4.c214 u32 pl_intr; in t1_mc4_intr_enable() local
219 pl_intr = t1_read_reg_4(mc4->adapter, A_PL_ENABLE); in t1_mc4_intr_enable()
221 pl_intr | F_PL_INTR_MC4); in t1_mc4_intr_enable()
227 u32 pl_intr; in t1_mc4_intr_disable() local
232 pl_intr = t1_read_reg_4(mc4->adapter, A_PL_ENABLE); in t1_mc4_intr_disable()
234 pl_intr & ~F_PL_INTR_MC4); in t1_mc4_intr_disable()
H A Dpm3393.c127 u32 pl_intr; in pm3393_interrupt_enable() local
167 pl_intr = t1_read_reg_4(cmac->adapter, A_PL_ENABLE); in pm3393_interrupt_enable()
168 pl_intr |= F_PL_INTR_EXT; in pm3393_interrupt_enable()
169 t1_write_reg_4(cmac->adapter, A_PL_ENABLE, pl_intr); in pm3393_interrupt_enable()
215 u32 pl_intr; in pm3393_interrupt_clear() local
249 pl_intr = t1_read_reg_4(cmac->adapter, A_PL_CAUSE); in pm3393_interrupt_clear()
250 pl_intr |= F_PL_INTR_EXT; in pm3393_interrupt_clear()
251 t1_write_reg_4(cmac->adapter, A_PL_CAUSE, pl_intr); in pm3393_interrupt_clear()
H A Despi.c129 u32 enable, pl_intr = t1_read_reg_4(espi->adapter, A_PL_ENABLE); in t1_espi_intr_enable() local
140 t1_write_reg_4(espi->adapter, A_PL_ENABLE, pl_intr | F_PL_INTR_ESPI); in t1_espi_intr_enable()
152 u32 pl_intr = t1_read_reg_4(espi->adapter, A_PL_ENABLE); in t1_espi_intr_disable() local
155 t1_write_reg_4(espi->adapter, A_PL_ENABLE, pl_intr & ~F_PL_INTR_ESPI); in t1_espi_intr_disable()
H A Dmc3.c65 u32 pl_intr = t1_read_reg_4(mc3->adapter, A_PL_ENABLE); in t1_mc3_intr_disable() local
70 pl_intr & ~F_PL_INTR_MC3); in t1_mc3_intr_disable()
75 pl_intr & ~FPGA_PCIX_INTERRUPT_MC3); in t1_mc3_intr_disable()
H A Dmc5.c520 u32 pl_intr = t1_read_reg_4(mc5->adapter, A_PL_ENABLE); in t1_mc5_intr_enable() local
523 pl_intr | F_PL_INTR_MC5); in t1_mc5_intr_enable()
538 u32 pl_intr = t1_read_reg_4(mc5->adapter, A_PL_ENABLE); in t1_mc5_intr_disable() local
541 pl_intr & ~F_PL_INTR_MC5); in t1_mc5_intr_disable()
H A Dch_subr.c1012 u32 pl_intr = t1_read_reg_4(adapter, A_PL_ENABLE); in t1_interrupts_enable() local
1019 pl_intr |= F_PL_INTR_EXT | F_PL_INTR_PCIX; in t1_interrupts_enable()
1020 t1_write_reg_4(adapter, A_PL_ENABLE, pl_intr); in t1_interrupts_enable()
1090 u32 pl_intr = t1_read_reg_4(adapter, A_PL_CAUSE); in t1_interrupts_clear() local
1093 pl_intr | F_PL_INTR_EXT | F_PL_INTR_PCIX); in t1_interrupts_clear()