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Searched refs:phy_addr (Results 1 – 25 of 37) sorted by relevance

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/titanic_41/usr/src/grub/grub-0.97/netboot/
H A Dsis900.c83 static void sis900_read_mode(struct nic *nic, int phy_addr, int *speed, int *duplex);
84 static void amd79c901_read_mode(struct nic *nic, int phy_addr, int *speed, int *duplex);
85 static void ics1893_read_mode(struct nic *nic, int phy_addr, int *speed, int *duplex);
86 static void rtl8201_read_mode(struct nic *nic, int phy_addr, int *speed, int *duplex);
87 static void vt6103_read_mode(struct nic *nic, int phy_addr, int *speed, int *duplex);
93 void (*read_mode) (struct nic *nic, int phy_addr, int *speed, int *duplex);
108 int phy_addr; member
321 int phy_addr; in sis900_probe() local
373 for (phy_addr = 0; phy_addr < 32; phy_addr++) { in sis900_probe()
377 mii_status = sis900_mdio_read(phy_addr, MII_STATUS); in sis900_probe()
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H A Ddavicom.c210 int i, phy_addr=1; in phy_read() local
232 phy_write_1bit(io_dcr9, phy_addr&i ? PHY_DATA_1: PHY_DATA_0); in phy_read()
255 u16 i, phy_addr=1; in phy_write() local
276 phy_write_1bit(io_dcr9, phy_addr&i ? PHY_DATA_1: PHY_DATA_0); in phy_write()
H A De1000.c2841 const uint32_t phy_addr = 1; local
2856 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2894 mdic = ((reg_addr) | (phy_addr << 5) |
2944 const uint32_t phy_addr = 1; local
2960 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2989 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
/titanic_41/usr/src/uts/common/io/chxge/com/
H A Dcphy.h35 int (*read)(adapter_t *adapter, int phy_addr, int mmd_addr,
37 int (*write)(adapter_t *adapter, int phy_addr, int mmd_addr,
92 int (*mdio_read)(adapter_t *adapter, int phy_addr, int mmd_addr,
94 int (*mdio_write)(adapter_t *adapter, int phy_addr, int mmd_addr,
126 int phy_addr, struct cphy_ops *phy_ops, in cphy_init() argument
130 phy->addr = phy_addr; in cphy_init()
141 struct cphy *(*create)(adapter_t *adapter, int phy_addr,
H A Dch_subr.c276 static int fpga_mdio_read(adapter_t *adapter, int phy_addr, int mmd_addr, in fpga_mdio_read() argument
289 V_MI0_PHY_REG_ADDR(reg_addr) | V_MI0_PHY_ADDR(phy_addr)); in fpga_mdio_read()
295 static int fpga_mdio_write(adapter_t *adapter, int phy_addr, int mmd_addr, in fpga_mdio_write() argument
308 V_MI0_PHY_REG_ADDR(reg_addr) | V_MI0_PHY_ADDR(phy_addr)); in fpga_mdio_write()
359 static int mi1_mdio_read(adapter_t *adapter, int phy_addr, int mmd_addr, in mi1_mdio_read() argument
362 u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr); in mi1_mdio_read()
377 static int mi1_mdio_write(adapter_t *adapter, int phy_addr, int mmd_addr, in mi1_mdio_write() argument
380 u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr); in mi1_mdio_write()
406 static int mi1_mdio_ext_readinc(adapter_t *adapter, int phy_addr, int mmd_addr,
409 u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr);
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H A Dmv88x201x.c218 static struct cphy *mv88x201x_phy_create(adapter_t *adapter, int phy_addr, in mv88x201x_phy_create() argument
227 cphy_init(cphy, adapter, phy_addr, &mv88x201x_ops, mdio_ops); in mv88x201x_phy_create()
H A Dmy3126.c199 static struct cphy *my3126_phy_create(adapter_t *adapter, int phy_addr, in my3126_phy_create() argument
205 cphy_init(cphy, adapter, phy_addr, &my3126_ops, mdio_ops); in my3126_phy_create()
H A Dxpak.c110 static struct cphy *xpak_phy_create(adapter_t * adapter, int phy_addr, in xpak_phy_create() argument
H A Dmv88e1xxx.c397 static struct cphy *mv88e1xxx_phy_create(adapter_t *adapter, int phy_addr, in mv88e1xxx_phy_create() argument
404 cphy_init(cphy, adapter, phy_addr, &mv88e1xxx_ops, mdio_ops); in mv88e1xxx_phy_create()
/titanic_41/usr/src/uts/common/io/cpqary3/
H A Dcpqary3_talk2ctlr.c441 uint32_t phy_addr; in cpqary3_init_ctlr() local
684 phy_addr = 0; in cpqary3_init_ctlr()
686 cmd_size, &phy_addr, cpqary3_phyctgp); in cpqary3_init_ctlr()
702 cpqary3p->drvr_replyq->replyq_start_paddr = phy_addr; in cpqary3_init_ctlr()
704 DDI_PUT32_CP(cpqary3p, &perf_cfg->ReplyQAddr0Low32, phy_addr); in cpqary3_init_ctlr()
/titanic_41/usr/src/uts/common/io/i40e/core/
H A Di40e_common.c5968 u16 reg, u8 phy_addr, u16 *value) in i40e_read_phy_register_clause22() argument
5976 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | in i40e_read_phy_register_clause22()
6013 u16 reg, u8 phy_addr, u16 value) in i40e_write_phy_register_clause22() argument
6024 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | in i40e_write_phy_register_clause22()
6054 u8 page, u16 reg, u8 phy_addr, u16 *value) in i40e_read_phy_register_clause45() argument
6063 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | in i40e_read_phy_register_clause45()
6086 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | in i40e_read_phy_register_clause45()
6128 u8 page, u16 reg, u8 phy_addr, u16 value) in i40e_write_phy_register_clause45() argument
6137 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | in i40e_write_phy_register_clause45()
6162 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | in i40e_write_phy_register_clause45()
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H A Di40e_prototype.h521 u16 reg, u8 phy_addr, u16 *value);
523 u16 reg, u8 phy_addr, u16 value);
525 u8 page, u16 reg, u8 phy_addr, u16 *value);
527 u8 page, u16 reg, u8 phy_addr, u16 value);
529 u8 page, u16 reg, u8 phy_addr, u16 *value);
531 u8 page, u16 reg, u8 phy_addr, u16 value);
/titanic_41/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/
H A Dbnxe_context.c577 lm_address_t phy_addr = {{0}} ; in lm_allocate_cid() local
649 phy_addr.as_u32.low = (pdev->hw_info.mem_base[BAR_1].as_u32.low) & 0xfffffff0; in lm_allocate_cid()
650 phy_addr.as_u32.high = pdev->hw_info.mem_base[BAR_1].as_u32.high; in lm_allocate_cid()
652 LM_INC64(&phy_addr,(cid*LM_DQ_CID_SIZE)); in lm_allocate_cid()
662 phy_addr, in lm_allocate_cid()
675 (volatile void *)mm_map_io_space(pdev, phy_addr, LM_DQ_CID_SIZE); in lm_allocate_cid()
683 …d: mm_map_io_space failed. address low=%d address high=%d\n", phy_addr.as_u32.low,phy_addr.as_u32.… in lm_allocate_cid()
H A Dlm_phy.c263 tmp = (pdev->vars.phy_addr << 21) | (reg << 16) | (val & EMAC_MDIO_COMM_DATA) | in lm_mwrite()
337 val = (pdev->vars.phy_addr << 21) | (reg << 16) | in lm_mread()
390 u8_t phy_addr, in lm_phy45_read() argument
401 rc = elink_phy_read(&pdev->params.link, phy_addr, dev_addr, reg, ret_val); in lm_phy45_read()
418 u8_t phy_addr, in lm_phy45_write() argument
429 rc = elink_phy_write(&pdev->params.link, phy_addr, dev_addr, reg, val); in lm_phy45_write()
447 pdev->vars.phy_addr = addr; in lm_set_phy_addr()
/titanic_41/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A Dclc.h211 #define ELINK_FW_PARAM_SET(phy_addr, phy_type, mdio_access) \ argument
212 (phy_addr | phy_type | mdio_access << ELINK_FW_PARAM_MDIO_CTRL_OFFSET)
528 elink_status_t elink_phy_read(struct elink_params *params, u8 phy_addr,
531 elink_status_t elink_phy_write(struct elink_params *params, u8 phy_addr,
/titanic_41/usr/src/uts/common/io/ixgbe/
H A Dixgbe_phy.c92 u32 phy_addr; in ixgbe_identify_phy_generic() local
98 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { in ixgbe_identify_phy_generic()
99 if (ixgbe_validate_phy_addr(hw, phy_addr)) { in ixgbe_identify_phy_generic()
100 hw->phy.addr = phy_addr; in ixgbe_identify_phy_generic()
139 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) in ixgbe_validate_phy_addr() argument
146 hw->phy.addr = phy_addr; in ixgbe_validate_phy_addr()
H A Dixgbe_phy.h99 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);
/titanic_41/usr/src/uts/common/io/e1000api/
H A De1000_phy.c3058 u32 phy_addr = 0; in e1000_determine_phy_address() local
3064 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { in e1000_determine_phy_address()
3065 hw->phy.addr = phy_addr; in e1000_determine_phy_address()
3094 u32 phy_addr = 2; in e1000_get_phy_addr_for_bm_page() local
3097 phy_addr = 1; in e1000_get_phy_addr_for_bm_page()
3099 return phy_addr; in e1000_get_phy_addr_for_bm_page()
3538 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); in __e1000_read_phy_reg_hv() local
3570 hw->phy.addr = phy_addr; in __e1000_read_phy_reg_hv()
3648 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); in __e1000_write_phy_reg_hv() local
3696 hw->phy.addr = phy_addr; in __e1000_write_phy_reg_hv()
[all …]
/titanic_41/usr/src/uts/common/io/mii/
H A Dmiipriv.h50 uint8_t phy_addr; member
H A Dmii.c281 mh->m_bogus_phy.phy_addr = 0xff; in mii_alloc_instance()
946 *val = ph->phy_addr; in mii_m_getstat()
1067 return ((*mh->m_ops.mii_read)(mh->m_private, ph->phy_addr, reg)); in phy_read()
1075 (*mh->m_ops.mii_write)(mh->m_private, ph->phy_addr, reg, val); in phy_write()
1837 ph->phy_addr = curr_addr; in _mii_probe()
/titanic_41/usr/src/uts/intel/io/amd8111s/
H A Damd8111s_main.h246 uint64_t phy_addr; member
/titanic_41/usr/src/uts/common/io/cxgbe/common/
H A Dcommon.h472 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
474 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
/titanic_41/usr/src/uts/common/io/fibre-channel/fca/qlge/
H A Dqlge_dbg.c2625 uint64_t timestamp, phy_addr; in ql_8xxx_binary_core_dump() local
2924 phy_addr = qlge->ioctl_buf_dma_attr.dma_addr; in ql_8xxx_binary_core_dump()
2925 if (ql_read_risc_ram(qlge, CODE_RAM_ADDR, phy_addr, CODE_RAM_CNT) in ql_8xxx_binary_core_dump()
2943 phy_addr = qlge->ioctl_buf_dma_attr.dma_addr; in ql_8xxx_binary_core_dump()
2944 if (ql_read_risc_ram(qlge, MEMC_RAM_ADDR, phy_addr, MEMC_RAM_CNT) in ql_8xxx_binary_core_dump()
/titanic_41/usr/src/uts/common/io/ntxn/
H A Dniu.c135 address.phy_addr = (unm_crbword_t)phy; in unm_niu_gbe_phy_read()
/titanic_41/usr/src/uts/intel/io/dnet/
H A Ddnet.c191 static ushort_t dnet_mii_read(dev_info_t *dip, int phy_addr, int reg_num);
192 static void dnet_mii_write(dev_info_t *dip, int phy_addr, int reg_num,
3819 dnet_mii_read(dev_info_t *dip, int phy_addr, int reg_num) in dnet_mii_read() argument
3837 command_word = (uint32_t)phy_addr << MII_PHY_ADDR_ALIGN; in dnet_mii_read()
3869 dnet_mii_write(dev_info_t *dip, int phy_addr, int reg_num, int reg_dat) in dnet_mii_write() argument
3881 command_word = ((uint32_t)phy_addr << MII_PHY_ADDR_ALIGN); in dnet_mii_write()

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