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Searched refs:outl (Results 1 – 25 of 41) sorted by relevance

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/titanic_41/usr/src/grub/grub-0.97/netboot/
H A Dtulip.c579 outl(0x60020000 + (phy_id<<23) + (location<<18), ioaddr + 0xA0); in mdio_read()
602 outl(MDIO_ENB | MDIO_DATA_WRITE1, mdio_addr); in mdio_read()
604 outl(MDIO_ENB | MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr); in mdio_read()
611 outl(MDIO_ENB | dataval, mdio_addr); in mdio_read()
613 outl(MDIO_ENB | dataval | MDIO_SHIFT_CLK, mdio_addr); in mdio_read()
618 outl(MDIO_ENB_IN, mdio_addr); in mdio_read()
621 outl(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr); in mdio_read()
639 outl(cmd, ioaddr + 0xA0); in mdio_write()
651 outl(value, ioaddr + 0xB4 + (location<<2)); in mdio_write()
653 outl(value, ioaddr + 0xD0); in mdio_write()
[all …]
H A Dsis900.c208 outl(EEREQ, ee_addr); in sis96x_get_mac_addr()
216 outl(EEDONE, ee_addr); in sis96x_get_mac_addr()
223 outl(EEDONE, ee_addr); in sis96x_get_mac_addr()
284 outl(rfcrSave | RELOAD, ioaddr + cr); in sis635_get_mac_addr()
285 outl(0, ioaddr + cr); in sis635_get_mac_addr()
288 outl(rfcrSave & ~RFEN, rfcr + ioaddr); in sis635_get_mac_addr()
292 outl((i << RFADDR_shift), ioaddr + rfcr); in sis635_get_mac_addr()
297 outl(rfcrSave | RFEN, rfcr + ioaddr); in sis635_get_mac_addr()
363 outl(ACCESSMODE | inl(ioaddr + cr), ioaddr + cr); in sis900_probe()
452 outl(0, ee_addr); in sis900_read_eeprom()
[all …]
H A Dnatsemi.c291 outl(ChipReset, ioaddr + ChipCmd); in natsemi_probe()
313 outl(SavedClkRun & ~0x100, ioaddr + ClkRun); in natsemi_probe()
356 outl(EE_Write0, ee_addr); in eeprom_read()
361 outl(dataval, ee_addr); in eeprom_read()
363 outl(dataval | EE_ShiftClk, ee_addr); in eeprom_read()
366 outl(EE_ChipSelect, ee_addr); in eeprom_read()
370 outl(EE_ChipSelect | EE_ShiftClk, ee_addr); in eeprom_read()
373 outl(EE_ChipSelect, ee_addr); in eeprom_read()
378 outl(EE_Write0, ee_addr); in eeprom_read()
379 outl(0, ee_addr); in eeprom_read()
[all …]
H A Depic100.c135 outl(GC_SOFT_RESET, genctl); in epic100_probe()
138 outl(INTR_DISABLE, intmask); in epic100_probe()
154 outl(0x00000008, test); in epic100_probe()
217 outl(0x0C, rxcon); in set_rx_mode()
233 outl(GC_RX_FIFO_THR_64 | GC_MRC_READ_MULT | GC_ONE_COPY, genctl); in epic100_open()
235 outl(TX_FIFO_THRESH, eththr); in epic100_open()
247 outl(tmp, txcon); in epic100_open()
250 outl(virt_to_le32desc(&rx_ring), prcdar); in epic100_open()
251 outl(virt_to_le32desc(&tx_ring), ptcdar); in epic100_open()
255 outl(CR_START_RX | CR_QUEUE_RX, command); in epic100_open()
[all …]
H A Ddavicom.c297 outl(phy_data, ee_addr); /* MII Clock Low */ in phy_write_1bit()
299 outl(phy_data|MDCLKH, ee_addr); /* MII Clock High */ in phy_write_1bit()
301 outl(phy_data, ee_addr); /* MII Clock Low */ in phy_write_1bit()
314 outl(0x50000, ee_addr); in phy_read_1bit()
319 outl(0x40000, ee_addr); in phy_read_1bit()
355 outl(csr6, ioaddr + CSR6); in davicom_media_chk()
374 outl(csr6, ioaddr + CSR6); in davicom_media_chk()
398 outl(EE_ENB & ~EE_CS, ee_addr); in read_eeprom()
399 outl(EE_ENB, ee_addr); in read_eeprom()
404 outl(EE_ENB | dataval, ee_addr); in read_eeprom()
[all …]
H A Deepro100.c290 outl(0x04000000 | (location<<16) | (phy_id<<21) | value, in mdio_write()
312 outl(0x08000000 | (location<<16) | (phy_id<<21), ioaddr + SCBCtrlMDI); in mdio_read()
428 outl(virt_to_bus(&txfd), ioaddr + SCBPointer); in eepro100_transmit()
516 outl(virt_to_bus(&(ACCESS(rxfd)status)), ioaddr + SCBPointer); in eepro100_poll()
541 outl(0, ioaddr + SCBPort); in eepro100_disable()
545 outl(2, ioaddr + SCBPort); in eepro100_disable()
621 outl(0, ioaddr + SCBPort); in eepro100_probe()
626 outl(0, ioaddr + SCBPointer); in eepro100_probe()
631 outl(virt_to_bus(&lstats), ioaddr + SCBPointer); in eepro100_probe()
644 outl(virt_to_bus(&(ACCESS(rxfd)status)), ioaddr + SCBPointer); in eepro100_probe()
[all …]
H A Dpci_io.c31 outl(CONFIG_CMD(bus,device_fn,where), 0xCF8); in pcibios_read_config_byte()
39 outl(CONFIG_CMD(bus,device_fn,where), 0xCF8); in pcibios_read_config_word()
47 outl(CONFIG_CMD(bus,device_fn,where), 0xCF8); in pcibios_read_config_dword()
55 outl(CONFIG_CMD(bus,device_fn,where), 0xCF8); in pcibios_write_config_byte()
63 outl(CONFIG_CMD(bus,device_fn,where), 0xCF8); in pcibios_write_config_word()
70 outl(CONFIG_CMD(bus,device_fn,where), 0xCF8); in pcibios_write_config_dword()
71 outl(value, 0xCFC); in pcibios_write_config_dword()
H A Drtl8139.c304 outl(rtl8139_rx_config | rx_mode, nic->ioaddr + RxConfig); in set_rx_mode()
306 outl(mc_filter[0], nic->ioaddr + MAR0 + 0); in set_rx_mode()
307 outl(mc_filter[1], nic->ioaddr + MAR0 + 4); in set_rx_mode()
330 outl((RX_FIFO_THRESH<<13) | (RX_BUF_LEN_IDX<<11) | (RX_DMA_BURST<<8), in rtl_reset()
332 outl((TX_DMA_BURST<<8)|0x03000000, nic->ioaddr + TxConfig); in rtl_reset()
345 outl((unsigned long)virt_to_bus(rx_ring), nic->ioaddr + RxBuf); in rtl_reset()
355 outl(rtl8139_rx_config, nic->ioaddr + RxConfig); in rtl_reset()
358 outl(0, nic->ioaddr + RxMissed); in rtl_reset()
391 outl((unsigned long)virt_to_bus(tx_buffer), nic->ioaddr + TxAddr0 + cur_tx*4); in rtl_transmit()
392 outl(((TX_FIFO_THRESH<<11) & 0x003f0000) | len, in rtl_transmit()
H A Dtlan.c346 outl(data, BASE + TLAN_HOST_CMD); in TLan_ResetAdapter()
354 outl(data, BASE + TLAN_HOST_CMD); in TLan_ResetAdapter()
369 outl(TLAN_HC_LD_TMR | 0x3f, BASE + TLAN_HOST_CMD); in TLan_ResetAdapter()
370 outl(TLAN_HC_LD_THR | 0x0, BASE + TLAN_HOST_CMD); in TLan_ResetAdapter()
511 outl(virt_to_bus(&rx_ring), BASE + TLAN_CH_PARM); in TLan_FinishReset()
512 outl(TLAN_HC_GO | TLAN_HC_RT, BASE + TLAN_HOST_CMD); in TLan_FinishReset()
577 outl(host_cmd, BASE + TLAN_HOST_CMD); in tlan_poll()
581 outl(host_cmd, BASE + TLAN_HOST_CMD); in tlan_poll()
698 outl(virt_to_le32desc(tail_list), BASE + TLAN_CH_PARM); in tlan_transmit()
699 outl(TLAN_HC_GO, BASE + TLAN_HOST_CMD); in tlan_transmit()
[all …]
H A Dpcnet32.c349 outl(index, addr + PCNET32_DWIO_RAP); in pcnet32_dwio_read_csr()
355 outl(index, addr + PCNET32_DWIO_RAP); in pcnet32_dwio_write_csr()
356 outl(val, addr + PCNET32_DWIO_RDP); in pcnet32_dwio_write_csr()
361 outl(index, addr + PCNET32_DWIO_RAP); in pcnet32_dwio_read_bcr()
367 outl(index, addr + PCNET32_DWIO_RAP); in pcnet32_dwio_write_bcr()
368 outl(val, addr + PCNET32_DWIO_BDP); in pcnet32_dwio_write_bcr()
378 outl(val, addr + PCNET32_DWIO_RAP); in pcnet32_dwio_write_rap()
388 outl(88, addr + PCNET32_DWIO_RAP); in pcnet32_dwio_check()
H A D3c90x.c423 outl(cfg, INF_3C90X.IOAddr + regInternalConfig_3_l); in a3c90x_reset()
520 outl(virt_to_bus(&(INF_3C90X.TransmitDPD)), in a3c90x_transmit()
624 outl(virt_to_bus(&(INF_3C90X.ReceiveUPD)), in a3c90x_poll()
915 outl(cfg, INF_3C90X.IOAddr + regInternalConfig_3_l); in a3c90x_probe()
H A Dvia-rhine.c939 outl(0xffffffff, byMAR0); in set_rx_mode()
940 outl(0xffffffff, byMAR4); in set_rx_mode()
1160 outl (virt_to_bus (tp->rx_ring), dwCurrentRxDescAddr); in rhine_reset()
1161 outl (virt_to_bus (tp->tx_ring), dwCurrentTxDescAddr); in rhine_reset()
H A Dsundance.c394 outl(virt_to_le32desc(&rx_ring[0]), BASE + RxListPtr); in sundance_reset()
412 outl(inl(BASE + ASICCtrl) | 0x0c, BASE + ASICCtrl); in sundance_reset()
542 outl(virt_to_le32desc(&tx_ring[0]), BASE + TxListPtr); in sundance_transmit()
/titanic_41/usr/src/lib/libkmf/libkmf/common/
H A Dpem_encode.c141 PEM_EncodeUpdate(PEM_ENCODE_CTX *ctx, unsigned char *out, int *outl, in PEM_EncodeUpdate() argument
147 *outl = 0; in PEM_EncodeUpdate()
181 *outl = total; in PEM_EncodeUpdate()
185 PEM_EncodeFinal(PEM_ENCODE_CTX *ctx, unsigned char *out, int *outl) in PEM_EncodeFinal() argument
195 *outl = ret; in PEM_EncodeFinal()
204 int nlen, n, i, j, outl; in Der2Pem() local
241 PEM_EncodeUpdate(&ctx, p, &outl, &(data[j]), n); in Der2Pem()
242 i += outl; in Der2Pem()
245 p += outl; in Der2Pem()
248 PEM_EncodeFinal(&ctx, p, &outl); in Der2Pem()
[all …]
/titanic_41/usr/src/uts/i86pc/os/
H A Dpci_mech1.c57 outl(PCI_CONFADD, PCI_CADDR1(bus, device, function, reg)); in pci_mech1_getb()
74 outl(PCI_CONFADD, PCI_CADDR1(bus, device, function, reg)); in pci_mech1_getw()
91 outl(PCI_CONFADD, PCI_CADDR1(bus, device, function, reg)); in pci_mech1_getl()
106 outl(PCI_CONFADD, PCI_CADDR1(bus, device, function, reg)); in pci_mech1_putb()
120 outl(PCI_CONFADD, PCI_CADDR1(bus, device, function, reg)); in pci_mech1_putw()
134 outl(PCI_CONFADD, PCI_CADDR1(bus, device, function, reg)); in pci_mech1_putl()
135 outl(PCI_CONFDATA, val); in pci_mech1_putl()
H A Dpci_mech1_amd.c105 outl(PCI_CONFADD, PCI_CADDR1_ECS(bus, device, function, reg)); in pci_mech1_amd_getb()
122 outl(PCI_CONFADD, PCI_CADDR1_ECS(bus, device, function, reg)); in pci_mech1_amd_getw()
139 outl(PCI_CONFADD, PCI_CADDR1_ECS(bus, device, function, reg)); in pci_mech1_amd_getl()
154 outl(PCI_CONFADD, PCI_CADDR1_ECS(bus, device, function, reg)); in pci_mech1_amd_putb()
168 outl(PCI_CONFADD, PCI_CADDR1_ECS(bus, device, function, reg)); in pci_mech1_amd_putw()
182 outl(PCI_CONFADD, PCI_CADDR1_ECS(bus, device, function, reg)); in pci_mech1_amd_putl()
183 outl(PCI_CONFDATA, val); in pci_mech1_amd_putl()
H A Dpci_neptune.c105 outl(PCI_CONFADD, PCI_CADDR1(0, 0, 0, PCI_CONF_VENID)); in pci_check_neptune()
108 outl(PCI_CONFADD, tmp); in pci_check_neptune()
134 outl(PCI_CONFADD, PCI_CADDR1(0, 0, 0, 0)); in pci_neptune_disable()
H A Dpci_mech2.c155 outl(PCI_CADDR2(device, reg), val); in pci_mech2_putl()
/titanic_41/usr/src/uts/i86pc/ml/
H A Damd64.il155 .inline outl,8
158 outl (%dx)
H A Dia32.il142 .inline outl,8
145 outl (%dx)
/titanic_41/usr/src/uts/intel/asm/
H A Dsunddi.h103 outl(int port, uint32_t value) in outl() function
/titanic_41/usr/src/uts/intel/ia32/os/
H A Dddi_i86.c557 outl((uintptr_t)addr, ddi_swap32(value)); in i_ddi_io_swap_put32()
853 outl(port, ddi_swap32(*h++)); in i_ddi_io_swap_rep_put32()
856 outl(port, ddi_swap32(*h++)); in i_ddi_io_swap_rep_put32()
1164 outl((uintptr_t)addr, value); in i_ddi_prot_io_put32()
1212 outl((uintptr_t)addr, ddi_swap32(value)); in i_ddi_prot_io_swap_put32()
1700 outl(port, *h++); in i_ddi_prot_io_rep_put32()
1703 outl(port, *h++); in i_ddi_prot_io_rep_put32()
1741 outl(port, ddi_swap32(*h++)); in i_ddi_prot_io_swap_rep_put32()
1744 outl(port, ddi_swap32(*h++)); in i_ddi_prot_io_swap_rep_put32()
/titanic_41/usr/src/cmd/mdb/intel/amd64/kmdb/
H A Dkmdb_asmutil.s165 outl (%dx)
/titanic_41/usr/src/cmd/mdb/intel/ia32/kmdb/
H A Dkmdb_asmutil.s179 outl (%dx)
/titanic_41/usr/src/uts/intel/sys/
H A Darchsystm.h106 extern void outl(int port, uint32_t value);

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