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Searched refs:mwl_ctl_write4 (Results 1 – 2 of 2) sorted by relevance

/titanic_41/usr/src/uts/common/io/mwl/
H A Dmwl.c830 mwl_ctl_write4(sc, MACREG_REG_H2A_INTERRUPT_EVENTS, ISR_RESET); in mwlFwReset()
838 mwl_ctl_write4(sc, 0x00006014, 0x33); in mwlPokeSdramController()
839 mwl_ctl_write4(sc, 0x00006018, 0xa3a2632); in mwlPokeSdramController()
840 mwl_ctl_write4(sc, 0x00006010, SDRAMSIZE_Addr); in mwlPokeSdramController()
851 mwl_ctl_write4(sc, MACREG_REG_GEN_PTR, sc->sc_cmd_dmaaddr); in mwlTriggerPciCmd()
854 mwl_ctl_write4(sc, MACREG_REG_INT_CODE, 0x00); in mwlTriggerPciCmd()
857 mwl_ctl_write4(sc, MACREG_REG_H2A_INTERRUPT_EVENTS, in mwlTriggerPciCmd()
887 mwl_ctl_write4(sc, MACREG_REG_INT_CODE, 0); in mwlSendBlock()
906 mwl_ctl_write4(sc, MACREG_REG_INT_CODE, 0); in mwlSendBlock2()
1008 mwl_ctl_write4(sc, MACREG_REG_A2H_INTERRUPT_CLEAR_SEL, in mwl_fwload()
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H A Dmwl_var.h583 #define mwl_ctl_write4(sc, off, x) \ macro