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Searched refs:mcpu_vcpu_info (Results 1 – 12 of 12) sorted by relevance

/titanic_41/usr/src/uts/i86xpv/os/
H A Dxpv_timestamp.c100 src = &CPU->cpu_m.mcpu_vcpu_info->time; in dtrace_xpv_getsystime()
H A Devtchn.c992 ASSERT(CPU->cpu_m.mcpu_vcpu_info->evtchn_upcall_mask != 0); in ec_wait_on_evtchn()
1260 volatile vcpu_info_t *vci = cpu->cpu_m.mcpu_vcpu_info; in xen_callback_handler()
1470 volatile vcpu_info_t *vci = CPU->cpu_m.mcpu_vcpu_info; in ec_unmask_evtchn()
H A Dmp_xen.c348 cp->cpu_m.mcpu_vcpu_info = in mach_cpucontext_alloc()
H A Dxen_machdep.c527 if (CPU->cpu_m.mcpu_vcpu_info->evtchn_upcall_mask == 0) { in xen_suspend_domain()
H A Dxpv_panic.c643 CPU->cpu_m.mcpu_vcpu_info->time.tsc_to_system_mul >> NSEC_SHIFT; in xpv_panic_time_init()
/titanic_41/usr/src/uts/i86pc/sys/
H A Dmachcpuvar.h124 struct vcpu_info *mcpu_vcpu_info; member
/titanic_41/usr/src/uts/i86xpv/io/psm/
H A Dxpv_uppc.c765 ASSERT(cpu->cpu_m.mcpu_vcpu_info->evtchn_upcall_mask != 0); in xen_uppc_intr_enter()
824 volatile vcpu_info_t *vci = cpu->cpu_m.mcpu_vcpu_info; in xen_uppc_setspl()
H A Dxpv_psm.c534 ASSERT(cpu->cpu_m.mcpu_vcpu_info->evtchn_upcall_mask != 0); in xen_psm_intr_enter()
596 volatile vcpu_info_t *vci = cpu->cpu_m.mcpu_vcpu_info; in xen_psm_setspl()
/titanic_41/usr/src/uts/i86pc/os/
H A Dmlsetup.c123 cpu[0]->cpu_m.mcpu_vcpu_info = &HYPERVISOR_shared_info->vcpu_info[0]; in mlsetup()
H A Dstartup.c1482 CPU->cpu_m.mcpu_vcpu_info = in startup_kmem()
2242 ASSERT(CPU->cpu_m.mcpu_vcpu_info->evtchn_upcall_mask == 0); in startup_end()
H A Dmp_machdep.c1216 vcpu_time_info_t *vti = &CPU->cpu_m.mcpu_vcpu_info->time; in mach_getcpufreq()
/titanic_41/usr/src/uts/i86pc/ml/
H A Doffsets.in229 cpu_m.mcpu_vcpu_info CPU_VCPU_INFO