Searched refs:mask_arr_val (Results 1 – 1 of 1) sorted by relevance
1824 u32_t mask_arr_val[MAX_ATTN_REGS] = {0}; in lm_handle_deassertion_processing() local1935 mask_arr_val[i] = attn_sig_af_inv_arr[i] & HW_INTERRUT_ASSERT_SET_0 & group_mask_arr[i]; in lm_handle_deassertion_processing()1937 mask_arr_val[i] = attn_sig_af_inv_arr[i] & HW_INTERRUT_ASSERT_SET_1 & group_mask_arr[i]; in lm_handle_deassertion_processing()1939 mask_arr_val[i] = attn_sig_af_inv_arr[i] & HW_INTERRUT_ASSERT_SET_2 & group_mask_arr[i]; in lm_handle_deassertion_processing()1941 mask_arr_val[i] = attn_sig_af_inv_arr[i] & HW_INTERRUT_ASSERT_SET_4 & group_mask_arr[i]; in lm_handle_deassertion_processing()1943 if (mask_arr_val[2] & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) { in lm_handle_deassertion_processing()1947 if ( (mask_arr_val[0]) || in lm_handle_deassertion_processing()1948 (mask_arr_val[1] & ~AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) || in lm_handle_deassertion_processing()1949 …(mask_arr_val[2] & ~(AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT | AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT… in lm_handle_deassertion_processing()1950 (mask_arr_val[4]) ) in lm_handle_deassertion_processing()[all …]