| /titanic_41/usr/src/uts/common/os/ |
| H A D | panic.c | 311 splx(ipltospl(CLOCK_LEVEL)); in panicsys()
380 splx(ipltospl(CLOCK_LEVEL)); in panicsys()
391 splx(ipltospl(CLOCK_LEVEL)); in panicsys()
409 splx(MIN(s, ipltospl(CLOCK_LEVEL))); in panicsys()
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| H A D | unix_bb.c | 117 lock_set_spl(&unix_bb_lock, ipltospl(NMI_LEVEL), &s);
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| H A D | softint.c | 191 (void *)ipltospl(SPL8)); in softcall_init()
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| H A D | logsubr.c | 200 log_freeq = log_makeq(LOG_MINFREE, LOG_MAXFREE, (void *)ipltospl(SPL8)); in log_init()
206 log_intrq = log_makeq(0, LOG_HIWAT, (void *)ipltospl(SPL8)); in log_init()
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| /titanic_41/usr/src/uts/i86pc/os/ |
| H A D | pci_cfgspace.c | 111 (ddi_iblock_cookie_t)ipltospl(15)); in pci_cfgspace_init()
113 (ddi_iblock_cookie_t)ipltospl(DISP_LEVEL)); in pci_cfgspace_init()
115 (ddi_iblock_cookie_t)ipltospl(15)); in pci_cfgspace_init()
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| H A D | mp_call.c | 83 int save_spl = splr(ipltospl(XC_HI_PIL)); in cpu_call()
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| H A D | x_call.c | 476 save_spl = splr(ipltospl(XC_HI_PIL)); in xc_common()
634 int save_spl = splr(ipltospl(XC_HI_PIL)); in xc_priority()
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| H A D | mp_startup.c | 368 cp->cpu_base_spl = ipltospl(LOCK_LEVEL); in mp_cpu_configure_common()
1723 splx(ipltospl(LOCK_LEVEL)); in mp_startup_common()
1806 ASSERT(cp->cpu_base_spl == ipltospl(LOCK_LEVEL)); in mp_startup_common()
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| /titanic_41/usr/src/uts/intel/sys/ |
| H A D | spl.h | 37 #define ipltospl(n) (n) macro
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| H A D | machlock.h | 67 #define SPIN_LOCK(pl) ((pl) > ipltospl(LOCK_LEVEL))
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| /titanic_41/usr/src/uts/sparc/sys/ |
| H A D | spl.h | 39 #define ipltospl(n) (n) macro
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| H A D | machlock.h | 63 #define SPIN_LOCK(pl) ((pl) > ipltospl(LOCK_LEVEL))
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| /titanic_41/usr/src/uts/i86pc/sys/ |
| H A D | clock.h | 98 ipltospl(XC_HI_PIL), oldsplp)
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| /titanic_41/usr/src/uts/sun/sys/ |
| H A D | zsdev.h | 271 #define ZS_PL ipltospl(SPL3) /* translates to SPARC IPL 6 */
272 #define ZS_PL_HI ipltospl(SPLTTY) /* translates to SPARC IPL 12 */
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| /titanic_41/usr/src/uts/i86pc/io/ |
| H A D | cbe.c | 164 return (splr(ipltospl(ipl))); in cbe_set_level()
303 s = splr(ipltospl(XC_HI_PIL)); in cbe_hres_tick()
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| /titanic_41/usr/src/uts/sun4u/os/ |
| H A D | mach_cpu_states.c | 293 if (spl == ipltospl(PIL_14)) { in panic_enter_hw()
312 } else if (spl == ipltospl(PIL_15)) { in panic_enter_hw()
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| /titanic_41/usr/src/uts/sun4/sys/ |
| H A D | clock.h | 168 ipltospl(CBE_HIGH_PIL), oldsplp)
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| /titanic_41/usr/src/uts/sun4u/io/pci/ |
| H A D | pci_sc.c | 106 (void *)ipltospl(XCALL_PIL)); in sc_create()
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| /titanic_41/usr/src/uts/common/disp/ |
| H A D | disp_lock.c | 88 lock_set_spl(lp, ipltospl(DISP_LEVEL), &curthread->t_oldspl); in disp_lock_enter()
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| /titanic_41/usr/src/uts/intel/ia32/os/ |
| H A D | cpc_subr.c | 65 return (ipltospl(APIC_PCINT_IPL)); in kcpc_hw_add_ovf_intr()
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| /titanic_41/usr/src/uts/sun4/os/ |
| H A D | cpu_states.c | 244 if ((s = getpil()) < ipltospl(12)) in debug_enter()
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| H A D | mp_states.c | 55 mutex_init(&cpu_idle_lock, NULL, MUTEX_SPIN, (void *)ipltospl(PIL_15)); in idlestop_init()
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| /titanic_41/usr/src/uts/common/ipp/ |
| H A D | ippconf.c | 278 (void *)ipltospl(LOCK_LEVEL)); in ipp_init()
1700 (void *)ipltospl(LOCK_LEVEL)); in ipp_stat_create()
3277 (void *)ipltospl(LOCK_LEVEL)); in init_mods()
3292 (void *)ipltospl(LOCK_LEVEL)); in init_mods()
3308 (void *)ipltospl(LOCK_LEVEL)); in init_actions()
3325 (void *)ipltospl(LOCK_LEVEL)); in init_actions()
3384 (void *)ipltospl(LOCK_LEVEL)); in mod_constructor()
3468 (void *)ipltospl(LOCK_LEVEL)); in action_constructor()
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| H A D | ipp_impl.h | 117 (void *)ipltospl(LOCK_LEVEL)); \
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| /titanic_41/usr/src/uts/sun4u/opl/io/pcicmu/ |
| H A D | pcmu_pbm.c | 131 (void *)(uintptr_t)ipltospl(spltoipl( in pcmu_pbm_register_intr()
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