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Searched refs:iommu_ctrl_reg (Results 1 – 6 of 6) sorted by relevance

/titanic_41/usr/src/uts/sun4u/io/pci/
H A Dpci_iommu.c81 iommu_p->iommu_ctrl_reg = in iommu_create()
120 iommu_p->iommu_ctrl_reg, iommu_p->iommu_tsb_base_addr_reg); in iommu_create()
178 volatile uint64_t ctl_val = *iommu_p->iommu_ctrl_reg; in iommu_destroy()
188 *iommu_p->iommu_ctrl_reg = ctl_val; in iommu_destroy()
241 *iommu_p->iommu_ctrl_reg = COMMON_IOMMU_CTRL_DIAG_ENABLE; in iommu_configure()
467 uint64_t base = (uint64_t)(iommu_p->iommu_ctrl_reg) - in iommu_tlb_flushall()
484 uint64_t ctl = *iommu_p->iommu_ctrl_reg; in iommu_preserve_tsb()
H A Dpcisch.c2153 if (!((stat = *iommu_p->iommu_ctrl_reg) & TOMATILLO_IOMMU_ERR)) { in iommu_err_handler()
2595 pbm_err_p->pbm_iommu.iommu_stat = *iommu_p->iommu_ctrl_reg; in pci_pbm_errstate_get()
2679 *iommu_p->iommu_ctrl_reg = pbm_err_p->pbm_iommu.iommu_stat; in pci_clear_error()
2944 uint64_t base = (uint64_t)iommu_p->iommu_ctrl_reg - in iommu_tlb_scrub()
3005 ctl_old = *iommu_p->iommu_ctrl_reg; in pci_iommu_disp()
3030 volatile uint64_t *iommu_ctl_p = iommu_p->iommu_ctrl_reg; in pci_iommu_config()
H A Dpcipsy.c1099 volatile uint64_t *iommu_ctl_p = iommu_p->iommu_ctrl_reg; in pci_iommu_config()
/titanic_41/usr/src/uts/sun4u/sys/pci/
H A Dpci_iommu.h130 volatile uint64_t *iommu_ctrl_reg; member
/titanic_41/usr/src/uts/sun4u/sys/
H A Dsysiosbus.h267 volatile uint64_t *iommu_ctrl_reg; member
/titanic_41/usr/src/uts/sun4u/io/
H A Diommu.c138 softsp->iommu_ctrl_reg = REG_ADDR(address, OFF_IOMMU_CTRL_REG); in iommu_init()
225 (void *)softsp->iommu_ctrl_reg, (void *)softsp->tsb_base_addr, in iommu_init()
243 *softsp->iommu_ctrl_reg &= in iommu_uninit()
286 *softsp->iommu_ctrl_reg = (uint64_t)(tsb_size << TSB_SIZE_SHIFT in iommu_resume_init()