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Searched refs:intr_state (Results 1 – 19 of 19) sorted by relevance

/titanic_41/usr/src/cmd/mdb/sparc/modules/intr/
H A Dintr.c50 uint_t intr_state; member
247 info.intr_state = niumx_state.niumx_ihtable[i].ih_state; in intr_niumx_walk_step()
334 info.intr_state = ih.ih_intr_state; in intr_pci_print_items()
436 info.intr_state = ih.ih_intr_state; in intr_px_print_items()
502 info.intr_state ? "enbl" : "disbl"); in intr_print_elements()
527 mdb_printf("State:\t\t%d (%s)\n", info.intr_state, in intr_print_elements()
528 info.intr_state ? "Enabled" : "Disabled"); in intr_print_elements()
/titanic_41/usr/src/uts/sun4v/io/
H A Dvnex.c221 int intr_state; in vnex_intr_dist() local
233 &intr_state) == H_EOK) && (intr_state == HV_INTR_NOTVALID)) in vnex_intr_dist()
245 (hvio_intr_getstate(vid_p->vid_ihdl, &intr_state) == in vnex_intr_dist()
246 H_EOK) && (intr_state == HV_INTR_DELIVERED_STATE)) { in vnex_intr_dist()
H A Dcnex.c363 int intr_state; in cnex_intr_new_cpu() local
367 rv = hvldc_intr_getvalid(ssp->cfghdl, iinfo->ino, &intr_state); in cnex_intr_new_cpu()
375 if (intr_state == HV_INTR_VALID) { in cnex_intr_new_cpu()
389 if (intr_state == HV_INTR_VALID) { in cnex_intr_new_cpu()
404 int rv, intr_state, retries; in cnex_intr_dis_wait() local
421 rv = hvldc_intr_getstate(ssp->cfghdl, iinfo->ino, &intr_state); in cnex_intr_dis_wait()
428 if (intr_state != HV_INTR_DELIVERED_STATE) in cnex_intr_dis_wait()
/titanic_41/usr/src/uts/sun4v/sys/
H A Dhypervisor_api.h403 int *intr_state);
404 extern uint64_t hvio_intr_setstate(uint64_t sysino, int intr_state);
451 int *intr_state);
453 int intr_state);
/titanic_41/usr/src/uts/sun4u/serengeti/sys/
H A Dsgsbbc_mailbox_priv.h147 } intr_state[SBBC_MBOX_INTR_TYPES]; member
/titanic_41/usr/src/uts/sun4/io/px/
H A Dpx_lib.h70 intr_state_t *intr_state);
72 intr_state_t intr_state);
H A Dpx_ioapi.h72 typedef enum intr_state { enum
H A Dpx_ib.c173 intr_state_t intr_state; in px_ib_intr_pend() local
184 &intr_state)) == DDI_SUCCESS) && in px_ib_intr_pend()
185 (intr_state == INTR_DELIVERED_STATE); /* */) { in px_ib_intr_pend()
/titanic_41/usr/src/uts/sun4u/sys/
H A Drmc_comm_dp.h165 uint_t *intr_state; /* interrupt handler state */ member
H A Dsysiosbus.h354 uint_t intr_state; member
/titanic_41/usr/src/uts/sun4u/serengeti/io/
H A Dsgsbbc_mailbox.c465 state = (uint_t *)&master_mbox->intr_state[i].mbox_intr_state; in sbbc_mbox_create()
466 lock = &master_mbox->intr_state[i].mbox_intr_lock; in sbbc_mbox_create()
741 mutex_enter(&master_mbox->intr_state[MBOX_MSGIN_INTR].mbox_intr_lock); in sbbc_mbox_msgin()
742 master_mbox->intr_state[MBOX_MSGIN_INTR].mbox_intr_state = in sbbc_mbox_msgin()
744 mutex_exit(&master_mbox->intr_state[MBOX_MSGIN_INTR].mbox_intr_lock); in sbbc_mbox_msgin()
769 mutex_enter(&master_mbox->intr_state[MBOX_MSGIN_INTR]. in sbbc_mbox_msgin()
776 mutex_exit(&master_mbox->intr_state[MBOX_MSGIN_INTR]. in sbbc_mbox_msgin()
779 master_mbox->intr_state[MBOX_MSGIN_INTR]. in sbbc_mbox_msgin()
781 mutex_exit(&master_mbox->intr_state[MBOX_MSGIN_INTR]. in sbbc_mbox_msgin()
/titanic_41/usr/src/uts/sun4u/io/px/
H A Dpx_lib4u.h312 intr_state_t *intr_state);
314 intr_state_t intr_state);
H A Dpx_lib4u.c398 intr_state_t *intr_state) in px_lib_intr_getstate() argument
406 sysino, intr_state)) != H_EOK) { in px_lib_intr_getstate()
413 *intr_state); in px_lib_intr_getstate()
421 intr_state_t intr_state) in px_lib_intr_setstate() argument
426 "intr_state 0x%x\n", dip, sysino, intr_state); in px_lib_intr_setstate()
429 sysino, intr_state)) != H_EOK) { in px_lib_intr_setstate()
H A Dpx_hlib.c2109 intr_state_t *intr_state) in hvio_intr_getstate() argument
2118 *intr_state = INTR_IDLE_STATE; in hvio_intr_getstate()
2121 *intr_state = INTR_RECEIVED_STATE; in hvio_intr_getstate()
2124 *intr_state = INTR_DELIVERED_STATE; in hvio_intr_getstate()
2143 intr_state_t intr_state) in hvio_intr_setstate() argument
2147 switch (intr_state) { in hvio_intr_setstate()
/titanic_41/usr/src/uts/sun4v/ml/
H A Dhcall.s135 hvio_intr_getstate(uint64_t sysino, int *intr_state)
140 hvio_intr_setstate(uint64_t sysino, int intr_state)
292 hvldc_intr_getstate(uint64_t dev_hdl, uint32_t devino, int *intr_state)
297 hvldc_intr_setstate(uint64_t dev_hdl, uint32_t devino, int intr_state)
/titanic_41/usr/src/uts/sun4v/io/px/
H A Dpx_lib4v.c321 intr_state_t *intr_state) in px_lib_intr_getstate() argument
328 if ((ret = hvio_intr_getstate(sysino, (int *)intr_state)) != H_EOK) { in px_lib_intr_getstate()
335 *intr_state); in px_lib_intr_getstate()
343 intr_state_t intr_state) in px_lib_intr_setstate() argument
348 "intr_state 0x%x\n", dip, sysino, intr_state); in px_lib_intr_setstate()
350 if ((ret = hvio_intr_setstate(sysino, intr_state)) != H_EOK) { in px_lib_intr_setstate()
/titanic_41/usr/src/uts/sun4u/io/
H A Drmc_comm_drvintf.c670 msgintr->intr_state = state; in rmc_comm_reg_intr()
712 msgintr->intr_state = NULL; in rmc_comm_unreg_intr()
H A Drmc_comm_dp.c1113 if (dmi->intr_state == NULL || in rmc_comm_dp_mrecv()
1114 (dmi->intr_state != NULL && in rmc_comm_dp_mrecv()
1115 *(dmi->intr_state) == RMC_COMM_INTR_IDLE)) { in rmc_comm_dp_mrecv()
H A Dsysiosbus.c1628 if (intr_handler->intr_state == SBUS_INTR_STATE_DISABLE) { in sbus_intr_wrapper()
2629 intr_handler->intr_state = new_intr_state; in sbus_update_intr_state()