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Searched refs:ih_pri (Results 1 – 25 of 37) sorted by relevance

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/titanic_41/usr/src/uts/sun4/io/px/
H A Dpx_intr.c500 *(int *)result = hdlp->ih_pri ? in px_intx_ops()
501 hdlp->ih_pri : pci_class_to_pil(rdip); in px_intx_ops()
520 hdlp->ih_vector, hdlp->ih_pri, PX_INTR_STATE_ENABLE, 0, 0); in px_intx_ops()
524 hdlp->ih_vector, hdlp->ih_pri, PX_INTR_STATE_DISABLE, 0, 0); in px_intx_ops()
644 *(int *)result = hdlp->ih_pri ? in px_msix_ops()
645 hdlp->ih_pri : pci_class_to_pil(rdip); in px_msix_ops()
678 px_msiqid_to_devino(px_p, msiq_id), hdlp->ih_pri, in px_msix_ops()
696 hdlp->ih_pri, PX_INTR_STATE_DISABLE, msiq_rec_type, in px_msix_ops()
969 if (hdlp->ih_pri == 0) in px_add_intx_intr()
970 hdlp->ih_pri = pci_class_to_pil(rdip); in px_add_intx_intr()
[all …]
H A Dpx_pec.c161 hdl.ih_pri = PX_ERR_LOW_PIL; in px_pec_msg_add_intr()
184 hdl.ih_pri = PX_ERR_PIL; in px_pec_msg_add_intr()
208 hdl.ih_pri = PX_ERR_PIL; in px_pec_msg_add_intr()
258 hdl.ih_pri = PX_ERR_LOW_PIL; in px_pec_msg_rem_intr()
275 hdl.ih_pri = PX_ERR_PIL; in px_pec_msg_rem_intr()
291 hdl.ih_pri = PX_ERR_PIL; in px_pec_msg_rem_intr()
H A Dpx_ib.c1016 px_msiqid_to_devino(px_p, msiq_id), hdlp->ih_pri, in px_ib_set_msix_target()
1043 hdlp->ih_pri), rdip, hdlp->ih_inum, msiq_rec_type, msi_num); in px_ib_set_msix_target()
1046 ih_p = px_ib_intr_locate_ih(px_ib_ino_locate_ipil(ino_p, hdlp->ih_pri), in px_ib_set_msix_target()
1200 hdlp->ih_pri = ipil_p->ipil_pil; in pxtool_ib_get_msi_info()
/titanic_41/usr/src/uts/sun4u/io/pci/
H A Dpci_intr.c520 if (ino_p && (ipil_p = ib_ino_locate_ipil(ino_p, hdlp->ih_pri))) { in pci_add_intr()
536 if (hdlp->ih_pri == 0) in pci_add_intr()
537 hdlp->ih_pri = pci_class_to_pil(rdip); in pci_add_intr()
539 ipil_p = ib_new_ino_pil(ib_p, ino, hdlp->ih_pri, ih_p); in pci_add_intr()
548 hdlp->ih_pri, hdlp->ih_vector); in pci_add_intr()
566 ipil_p->ipil_pil = hdlp->ih_pri; in pci_add_intr()
610 hdlp->ih_vector, hdlp->ih_pri); in pci_add_intr()
622 hdlp->ih_vector, hdlp->ih_pri); in pci_add_intr()
661 if (hdlp->ih_pri == 0) in pci_remove_intr()
662 hdlp->ih_pri = pci_class_to_pil(rdip); in pci_remove_intr()
[all …]
/titanic_41/usr/src/uts/sun4u/opl/io/pcicmu/
H A Dpcmu_intr.c222 hdlp->ih_pri, hdlp->ih_vector); in pcmu_add_intr()
240 ino_p->pino_pil = hdlp->ih_pri; in pcmu_add_intr()
259 hdlp->ih_vector, hdlp->ih_pri); in pcmu_add_intr()
270 hdlp->ih_vector, hdlp->ih_pri); in pcmu_add_intr()
/titanic_41/usr/src/uts/common/sys/
H A Dddi_intr_impl.h85 uint_t ih_pri; /* priority - bus dependent */ member
164 uint_t ih_pri; /* priority - bus dependent */ member
378 ASSERT(hdlp->ih_pri == hdlp->ih_main->ih_pri); \
/titanic_41/usr/src/uts/common/os/
H A Dddi_intr.c321 hdlp->ih_pri = pri; in ddi_intr_alloc()
549 if (hdlp->ih_pri) { in ddi_intr_get_pri()
550 *prip = hdlp->ih_pri; in ddi_intr_get_pri()
559 hdlp->ih_pri = *prip; in ddi_intr_get_pri()
590 if (pri == hdlp->ih_pri) { in ddi_intr_set_pri()
599 hdlp->ih_pri = pri; in ddi_intr_set_pri()
1068 hdlp->ih_pri = soft_pri; in ddi_intr_add_softint()
1150 *soft_prip = hdlp->ih_pri; in ddi_intr_get_softint_pri()
1180 orig_soft_pri = hdlp->ih_pri; in ddi_intr_set_softint_pri()
1181 hdlp->ih_pri = soft_pri; in ddi_intr_set_softint_pri()
[all …]
/titanic_41/usr/src/uts/sun4v/io/
H A Dvnex.c508 if (hdlp->ih_pri == 0) { in vnex_add_intr()
509 hdlp->ih_pri = vnex_get_pil(rdip); in vnex_add_intr()
556 *(int *)result = hdlp->ih_pri ? in vnex_intr_ops()
557 hdlp->ih_pri : vnex_get_pil(rdip); in vnex_intr_ops()
H A Dmach_rootnex.c109 return (hdlp->ih_pri); in rootnex_get_intr_pri()
/titanic_41/usr/src/uts/sun4/io/
H A Debus.c796 if (hdlp->ih_pri) in ebus_intr_ops()
815 hdlp->ih_pri = ebus_name_to_pil[i].pil; in ebus_intr_ops()
833 hdlp->ih_pri = ebus_device_type_to_pil[i].pil; in ebus_intr_ops()
845 if (hdlp->ih_pri == 0) { in ebus_intr_ops()
846 hdlp->ih_pri = 1; in ebus_intr_ops()
850 ddi_get_instance(dip), hdlp->ih_pri, ddi_driver_name(rdip), in ebus_intr_ops()
/titanic_41/usr/src/uts/i86pc/io/pcplusmp/
H A Dapic_introp.c770 ispec->intrspec_pri = hdlp->ih_pri; in apic_intr_ops()
808 hdlp->ih_scratch1, hdlp->ih_pri, in apic_intr_ops()
812 hdlp->ih_scratch1, hdlp->ih_pri, in apic_intr_ops()
817 hdlp->ih_pri, hdlp->ih_type); in apic_intr_ops()
820 *result = apic_navail_vector(dip, hdlp->ih_pri); in apic_intr_ops()
863 old_priority = hdlp->ih_pri; /* save old value */ in apic_intr_ops()
/titanic_41/usr/src/uts/sun4/os/
H A Dddi_impl.c739 if (hdlp->ih_pri == 0) in i_ddi_intr_ops()
740 hdlp->ih_pri = i_ddi_get_intr_pri(rdip, hdlp->ih_inum); in i_ddi_intr_ops()
790 if ((hdlp->ih_pri < 1) || (hdlp->ih_pri > PIL_MAX)) in i_ddi_add_ivintr()
791 hdlp->ih_pri = 1; in i_ddi_add_ivintr()
793 VERIFY(add_ivintr(hdlp->ih_vector, hdlp->ih_pri, in i_ddi_add_ivintr()
807 VERIFY(rem_ivintr(hdlp->ih_vector, hdlp->ih_pri) == 0); in i_ddi_rem_ivintr()
911 if ((hdlp->ih_private = (void *)add_softintr(hdlp->ih_pri, in i_ddi_add_softint()
959 ret = update_softint_pri((uint64_t)hdlp->ih_private, hdlp->ih_pri); in i_ddi_set_softint_pri()
/titanic_41/usr/src/uts/sun4u/montecarlo/io/
H A Dacebus.c706 if (hdlp->ih_pri) in acebus_intr_ops()
727 hdlp->ih_pri = acebus_name_to_pil[i].pil; in acebus_intr_ops()
746 hdlp->ih_pri = acebus_device_type_to_pil[i].pil; in acebus_intr_ops()
758 if (hdlp->ih_pri == 0) { in acebus_intr_ops()
759 hdlp->ih_pri = 1; in acebus_intr_ops()
762 ddi_get_instance(dip), hdlp->ih_pri, ddi_driver_name(rdip), in acebus_intr_ops()
/titanic_41/usr/src/uts/i86pc/io/pci/
H A Dpci_common.c328 hdlp->ih_pri = in pci_common_intr_ops()
332 hdlp->ih_pri = priority; in pci_common_intr_ops()
420 ispec->intrspec_pri = hdlp->ih_pri; in pci_common_intr_ops()
936 ispec->intrspec_pri = hdlp->ih_pri; in pci_enable_intr()
945 hdlp->ih_pri, irq)); in pci_enable_intr()
948 if (!add_avintr((void *)hdlp, hdlp->ih_pri, hdlp->ih_cb_func, in pci_enable_intr()
973 ispec->intrspec_pri = hdlp->ih_pri; in pci_disable_intr()
981 rem_avintr((void *)hdlp, hdlp->ih_pri, hdlp->ih_cb_func, irq); in pci_disable_intr()
H A Dpci_kstats.c145 pci_ks_template.ihks_pil.value.ui64 = ih_p->ih_pri; in pci_ih_ks_update()
/titanic_41/usr/src/uts/sun4v/io/niumx/
H A Dniumx_var.h70 int ih_pri; /* interrupt priority */ member
H A Dniumx.c1085 if (hdlp->ih_pri == 0) in niumx_add_intr()
1086 hdlp->ih_pri = NIUMX_DEFAULT_PIL; in niumx_add_intr()
1088 ih_p->ih_pri = hdlp->ih_pri; in niumx_add_intr()
/titanic_41/usr/src/uts/sun4u/io/
H A Dmach_rootnex.c93 hdlp->ih_pri = 5; in rootnex_add_intr_impl()
218 int pri = hdlp->ih_pri; in rootnex_get_intr_pri()
H A Dsysiosbus.c1715 &hdlp->ih_pri, softsp->intr_mapping_ign) == DDI_FAILURE) { in sbus_add_intr_impl()
1848 sbus_arg->pil = hdlp->ih_pri; in sbus_add_intr_impl()
1939 &hdlp->ih_pri, softsp->intr_mapping_ign) == DDI_FAILURE) { in sbus_remove_intr_impl()
2127 if (hdlp->ih_pri == 0) { in sbus_intr_ops()
2130 (uint32_t *)&hdlp->ih_vector, &hdlp->ih_pri, in sbus_intr_ops()
2134 *(int *)result = hdlp->ih_pri; in sbus_intr_ops()
2613 &hdlp->ih_pri, softsp->intr_mapping_ign) == DDI_FAILURE) { in sbus_update_intr_state()
H A Dsbbc.c625 if (hdlp->ih_pri == 0) { in sbbc_intr_ops()
626 hdlp->ih_pri = 0x1; in sbbc_intr_ops()
630 ddi_get_instance(dip), hdlp->ih_pri, in sbbc_intr_ops()
634 *(int *)result = hdlp->ih_pri; in sbbc_intr_ops()
H A Dupa64s.c731 *(int *)result = hdlp->ih_pri ? hdlp->ih_pri : 5; in upa64_intr_ops()
/titanic_41/usr/src/uts/common/xen/io/
H A Dxpvd.c652 hdlp->ih_pri, vector)); in xpvd_enable_intr()
655 if (!add_avintr((void *)hdlp, hdlp->ih_pri, hdlp->ih_cb_func, in xpvd_enable_intr()
682 rem_avintr((void *)hdlp, hdlp->ih_pri, hdlp->ih_cb_func, vector); in xpvd_disable_intr()
/titanic_41/usr/src/uts/i86xpv/io/psm/
H A Dxpv_psm.c688 hdlp->ih_scratch1, hdlp->ih_pri, in xen_intr_ops()
692 hdlp->ih_scratch1, hdlp->ih_pri, in xen_intr_ops()
697 hdlp->ih_pri, hdlp->ih_type); in xen_intr_ops()
/titanic_41/usr/src/uts/i86pc/os/
H A Dddi_impl.c884 ret = add_avsoftintr((void *)hdlp, hdlp->ih_pri, hdlp->ih_cb_func, in i_ddi_add_softint()
893 (void) rem_avsoftintr((void *)hdlp, hdlp->ih_pri, hdlp->ih_cb_func); in i_ddi_remove_softint()
906 update_avsoftintr_args((void *)hdlp, hdlp->ih_pri, arg2); in i_ddi_trigger_softint()
908 (*setsoftint)(hdlp->ih_pri, hdlp->ih_pending); in i_ddi_trigger_softint()
/titanic_41/usr/src/cmd/mdb/sparc/modules/intr/
H A Dintr.c250 info.pil = niumx_state.niumx_ihtable[i].ih_pri; in intr_niumx_walk_step()

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