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Searched refs:host_hw_state (Results 1 – 6 of 6) sorted by relevance

/titanic_41/usr/src/uts/intel/io/heci/
H A Dheci_interface.c111 write_heci_register(dev, H_CSR, dev->host_hw_state); in heci_set_csr_register()
112 dev->host_hw_state = read_heci_register(dev, H_CSR); in heci_set_csr_register()
123 dev->host_hw_state |= H_IE; in heci_csr_enable_interrupts()
135 dev->host_hw_state &= ~H_IE; in heci_csr_disable_interrupts()
152 read_ptr = (char)((dev->host_hw_state & H_CBRP) >> 8); in _host_get_filled_slots()
153 write_ptr = (char)((dev->host_hw_state & H_CBWP) >> 16); in _host_get_filled_slots()
170 dev->host_hw_state = read_heci_register(dev, H_CSR); in host_buffer_is_empty()
191 buffer_depth = (unsigned char)((dev->host_hw_state & H_CBD) >> 24); in count_empty_write_slots()
224 dev->host_hw_state = read_heci_register(dev, H_CSR); in heci_write_message()
225 DBG("host_hw_state = 0x%08x.\n", dev->host_hw_state); in heci_write_message()
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H A Dheci_init.c285 dev->host_hw_state = read_heci_register(dev, H_CSR); in heci_hw_init()
288 dev->host_hw_state, dev->me_hw_state); in heci_hw_init()
290 if ((dev->host_hw_state & H_IS) == H_IS) { in heci_hw_init()
300 dev->host_hw_state, dev->me_hw_state); in heci_hw_init()
316 if (!(((dev->host_hw_state & H_RDY) == H_RDY) && in heci_hw_init()
320 dev->host_hw_state, in heci_hw_init()
323 if (!(dev->host_hw_state & H_RDY) != H_RDY) in heci_hw_init()
337 dev->host_hw_state, dev->me_hw_state); in heci_hw_init()
352 dev->host_hw_state |= (H_RST | H_IG); in heci_hw_reset()
393 dev->host_hw_state = read_heci_register(dev, H_CSR); in heci_reset()
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H A Dheci_intr.c116 device->host_hw_state = read_heci_register(device, H_CSR); in heci_isr_interrupt()
118 if ((device->host_hw_state & H_IS) != H_IS) { in heci_isr_interrupt()
239 dev->host_hw_state = read_heci_register(dev, H_CSR); in heci_bh_process_device()
253 if ((dev->host_hw_state & H_RDY) == 0) { in heci_bh_process_device()
256 dev->host_hw_state |= (H_IE | H_IG | H_RDY); in heci_bh_process_device()
299 dev->host_hw_state = read_heci_register(dev, H_CSR); in heci_bh_process_device()
302 if ((dev->host_hw_state & H_IS) == H_IS) { in heci_bh_process_device()
959 } else if (*slots == ((dev->host_hw_state & H_CBD) >> 24)) { in _heci_bh_cmpl()
1054 } else if (*slots == ((dev->host_hw_state & H_CBD) >> 24)) { in _heci_bh_cmpl_iamthif()
H A Dio_heci.c776 (((dev->host_hw_state & H_CBD) >> 24) * in pthi_write()
779 (((dev->host_hw_state & H_CBD) >> 24) * in pthi_write()
H A Dheci_data_structures.h523 uint32_t host_hw_state; member
H A Dheci_main.c320 device->host_hw_state = read_heci_register(device, H_CSR); in heci_initialize()
1179 if (length > ((((dev->host_hw_state & H_CBD) >> 24) * in heci_write()
1183 (((dev->host_hw_state & H_CBD) >> 24) * in heci_write()