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Searched refs:hccr (Results 1 – 7 of 7) sorted by relevance

/titanic_41/usr/src/uts/common/io/fibre-channel/fca/qlc/
H A Dql_init.c289 WRT16_IO_REG(ha, hccr, HC_PAUSE_RISC); in ql_pci_sbus_config()
291 if ((RD16_IO_REG(ha, hccr) & HC_RISC_PAUSE) != in ql_pci_sbus_config()
311 WRT16_IO_REG(ha, hccr, HC_RELEASE_RISC); in ql_pci_sbus_config()
313 if ((RD16_IO_REG(ha, hccr) & HC_RISC_PAUSE) == in ql_pci_sbus_config()
2276 RD16_IO_REG(ha, hccr), in ql_chip_diag()
3567 WRT16_IO_REG(ha, hccr, HC_PAUSE_RISC); in ql_reset_chip()
3569 if ((RD16_IO_REG(ha, hccr) & HC_RISC_PAUSE) != 0) { in ql_reset_chip()
3616 WRT16_IO_REG(ha, hccr, HC_RESET_RISC); in ql_reset_chip()
3622 WRT16_IO_REG(ha, hccr, HC_RELEASE_RISC); in ql_reset_chip()
3625 WRT16_IO_REG(ha, hccr, HC_CLR_RISC_INT); in ql_reset_chip()
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H A Dql_isr.c213 WRT16_IO_REG(ha, hccr, in ql_isr_aif()
324 WRT16_IO_REG(ha, hccr, HC_CLR_RISC_INT); in ql_isr_aif()
489 WRT32_IO_REG(ha, hccr, in ql_isr_aif()
492 WRT16_IO_REG(ha, hccr, HC_CLR_RISC_INT); in ql_isr_aif()
508 mbx = RD16_IO_REG(ha, hccr); /* PCI posting */ in ql_isr_aif()
568 hccr_reg = RD16_IO_REG(ha, hccr); in ql_handle_uncommon_risc_intr()
645 WRT32_IO_REG(ha, hccr, HC24_CLR_RISC_INT); in ql_spurious_intr()
647 WRT16_IO_REG(ha, hccr, HC_CLR_RISC_INT); in ql_spurious_intr()
707 WRT32_IO_REG(ha, hccr, HC24_CLR_RISC_INT); in ql_mbx_completion()
709 WRT16_IO_REG(ha, hccr, HC_CLR_RISC_INT); in ql_mbx_completion()
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H A Dql_api.c2269 WRT32_IO_REG(ha, hccr, HC24_CLR_RISC_INT); in ql_quiesce()
2271 WRT32_IO_REG(ha, hccr, HC24_SET_HOST_INT); in ql_quiesce()
2276 WRT32_IO_REG(ha, hccr, in ql_quiesce()
2280 WRT32_IO_REG(ha, hccr, HC24_CLR_RISC_INT); in ql_quiesce()
2297 WRT16_IO_REG(ha, hccr, HC_RESET_RISC); in ql_quiesce()
2299 WRT16_IO_REG(ha, hccr, HC_RELEASE_RISC); in ql_quiesce()
4290 RD16_IO_REG(ha, hccr), in ql_port_manage()
12297 (void) sprintf(bp, "\nHCCR Register\n%08x\n", fw->hccr); in ql_24xx_ascii_fw_dump()
13177 WRT16_IO_REG(ha, hccr, HC_PAUSE_RISC); in ql_2200_binary_fw_dump()
13179 while ((RD16_IO_REG(ha, hccr) & HC_RISC_PAUSE) == 0) { in ql_2200_binary_fw_dump()
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H A Dql_mbx.c159 WRT32_IO_REG(ha, hccr, HC24_SET_HOST_INT); in ql_mailbox_command()
161 WRT16_IO_REG(ha, hccr, HC_SET_HOST_INT); in ql_mailbox_command()
/titanic_41/usr/src/uts/common/sys/fibre-channel/fca/qlc/
H A Dql_init.h752 uint32_t hccr; member
H A Dql_api.h480 uint16_t hccr; /* Host command & control register. */ member
/titanic_41/usr/src/cmd/mdb/common/modules/qlc/
H A Dqlc.c2127 mdb_printf("\nHCCR Register\n%08x\n", fw->hccr); in ql_24xx_dump_dcmd()