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Searched refs:dev_ctrl (Results 1 – 2 of 2) sorted by relevance

/titanic_41/usr/src/uts/common/io/pciex/
H A Dpcie.c1793 uint16_t device_mps, device_mps_cap, device_mrrs, dev_ctrl; in pcie_initchild_mps() local
1795 dev_ctrl = PCIE_CAP_GET(16, bus_p, PCIE_DEVCTL); in pcie_initchild_mps()
1798 dev_ctrl = (dev_ctrl & ~(PCIE_DEVCTL_MAX_READ_REQ_MASK | in pcie_initchild_mps()
1804 PCIE_CAP_PUT(16, bus_p, PCIE_DEVCTL, dev_ctrl); in pcie_initchild_mps()
1811 device_mrrs = (dev_ctrl & PCIE_DEVCTL_MAX_READ_REQ_MASK) >> in pcie_initchild_mps()
1829 dev_ctrl &= ~(PCIE_DEVCTL_MAX_READ_REQ_MASK | in pcie_initchild_mps()
1832 dev_ctrl |= ((device_mrrs << PCIE_DEVCTL_MAX_READ_REQ_SHIFT) | in pcie_initchild_mps()
1835 PCIE_CAP_PUT(16, bus_p, PCIE_DEVCTL, dev_ctrl); in pcie_initchild_mps()
/titanic_41/usr/src/uts/sun4u/io/px/
H A Dpx_lib4u.c2681 uint64_t dev_ctrl; in px_lib_set_root_complex_mps() local
2692 dev_ctrl = CSR_XR(csr_base, TLU_DEVICE_CONTROL); in px_lib_set_root_complex_mps()
2693 dev_ctrl |= (mps << TLU_DEVICE_CONTROL_MPS); in px_lib_set_root_complex_mps()
2695 CSR_XS(csr_base, TLU_DEVICE_CONTROL, dev_ctrl); in px_lib_set_root_complex_mps()