Searched refs:cl72_ctrl (Results 1 – 1 of 1) sorted by relevance
4032 u16 lane, i, cl72_ctrl, an_adv = 0, val; in elink_warpcore_enable_AN_KR() local4052 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl); in elink_warpcore_enable_AN_KR()4053 cl72_ctrl &= 0x08ff; in elink_warpcore_enable_AN_KR()4054 cl72_ctrl |= 0x3800; in elink_warpcore_enable_AN_KR()4056 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl); in elink_warpcore_enable_AN_KR()