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Searched refs:cfg_handle (Results 1 – 25 of 40) sorted by relevance

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/titanic_41/usr/src/uts/common/io/igb/
H A Digb_osdep.c51 pci_config_put16(OS_DEP(hw)->cfg_handle, reg, *value); in e1000_write_pci_cfg()
58 pci_config_get16(OS_DEP(hw)->cfg_handle, reg); in e1000_read_pci_cfg()
74 status = pci_lcap_locate((OS_DEP(hw))->cfg_handle, pcie_id, &pcie_cap); in e1000_read_pcie_cap_reg()
78 *value = pci_config_get16(OS_DEP(hw)->cfg_handle, in e1000_read_pcie_cap_reg()
98 status = pci_lcap_locate(OS_DEP(hw)->cfg_handle, pcie_id, &pcie_cap); in e1000_write_pcie_cap_reg()
102 pci_config_put16(OS_DEP(hw)->cfg_handle, in e1000_write_pcie_cap_reg()
H A De1000_osdep.h184 ddi_acc_handle_t cfg_handle; member
H A Digb_main.c473 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { in igb_attach()
540 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) { in igb_attach()
813 if (igb->osdep.cfg_handle != NULL) in igb_unconfigure()
814 pci_config_teardown(&igb->osdep.cfg_handle); in igb_unconfigure()
892 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); in igb_identify_hardware()
894 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); in igb_identify_hardware()
896 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); in igb_identify_hardware()
898 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); in igb_identify_hardware()
900 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); in igb_identify_hardware()
1639 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) in igb_reset()
[all …]
H A Digb_debug.c55 handle = igb->osdep.cfg_handle; in pci_dump()
/titanic_41/usr/src/uts/common/io/e1000g/
H A De1000g_osdep.c48 pci_config_put16(OS_DEP(hw)->cfg_handle, reg, *value); in e1000_write_pci_cfg()
55 pci_config_get16(OS_DEP(hw)->cfg_handle, reg); in e1000_read_pci_cfg()
111 *value = pci_config_get16(OS_DEP(hw)->cfg_handle, in e1000_read_pcie_cap_reg()
130 status = pci_lcap_locate(OS_DEP(hw)->cfg_handle, pcie_id, &pcie_cap); in e1000_write_pcie_cap_reg()
134 pci_config_put16(OS_DEP(hw)->cfg_handle, in e1000_write_pcie_cap_reg()
H A De1000g_debug.c377 handle = Adapter->osdep.cfg_handle; in pciconfig_dump()
541 ddi_acc_handle_t handle = Adapter->osdep.cfg_handle; in pciconfig_bar()
H A De1000_osdep.h197 ddi_acc_handle_t cfg_handle; member
/titanic_41/usr/src/uts/common/io/ixgbe/
H A Dixgbe_osdep.c35 return (pci_config_get16(OS_DEP(hw)->cfg_handle, reg)); in ixgbe_read_pci_cfg()
41 pci_config_put16(OS_DEP(hw)->cfg_handle, reg, val); in ixgbe_write_pci_cfg()
H A Dixgbe_osdep.h137 ddi_acc_handle_t cfg_handle; member
/titanic_41/usr/src/uts/common/io/
H A Dpcic.c853 &pcic->cfg_handle) != in pcic_attach()
891 (void *)pcic->cfg_handle, nr); in pcic_attach()
913 ddi_regs_map_free(&pcic->cfg_handle); in pcic_attach()
929 ddi_regs_map_free(&pcic->cfg_handle); in pcic_attach()
964 ddi_regs_map_free(&pcic->cfg_handle); in pcic_attach()
980 ddi_regs_map_free(&pcic->cfg_handle); in pcic_attach()
1010 ddi_regs_map_free(&pcic->cfg_handle); in pcic_attach()
1069 iline = cardbus_validate_iline(dip, pcic->cfg_handle); in pcic_attach()
1076 cfg = ddi_get8(pcic->cfg_handle, in pcic_attach()
1134 cfg = ddi_get8(pcic->cfg_handle, in pcic_attach()
[all …]
/titanic_41/usr/src/uts/i86xpv/io/psm/
H A Dxpv_uppc.c669 ddi_acc_handle_t cfg_handle; in xen_uppc_translate_irq() local
700 if (pci_config_setup(dip, &cfg_handle) != DDI_SUCCESS) in xen_uppc_translate_irq()
703 ipin = pci_config_get8(cfg_handle, PCI_CONF_IPIN) - PCI_INTA; in xen_uppc_translate_irq()
704 iline = pci_config_get8(cfg_handle, PCI_CONF_ILINE); in xen_uppc_translate_irq()
728 pci_config_put8(cfg_handle, in xen_uppc_translate_irq()
731 pci_config_teardown(&cfg_handle); in xen_uppc_translate_irq()
735 pci_config_teardown(&cfg_handle); in xen_uppc_translate_irq()
H A Dmp_platform_xpv.c730 ddi_acc_handle_t cfg_handle; in apic_introp_xlate() local
803 if (pci_config_setup(dip, &cfg_handle) != DDI_SUCCESS) in apic_introp_xlate()
805 ipin = pci_config_get8(cfg_handle, PCI_CONF_IPIN) - PCI_INTA; in apic_introp_xlate()
806 pci_config_teardown(&cfg_handle); in apic_introp_xlate()
/titanic_41/usr/src/uts/common/io/bge/
H A Dbge_chip2.c187 regval = pci_config_get16(bgep->cfg_handle, regno); in bge_cfg_clr16()
193 pci_config_put16(bgep->cfg_handle, regno, regval); in bge_cfg_clr16()
209 regval = pci_config_get32(bgep->cfg_handle, regno); in bge_cfg_clr32()
215 pci_config_put32(bgep->cfg_handle, regno, regval); in bge_cfg_clr32()
250 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); in bge_ind_get32()
251 val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR); in bge_ind_get32()
277 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); in bge_ind_put32()
278 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val); in bge_ind_put32()
293 pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT); in bge_pci_check()
360 handle = bgep->cfg_handle; in bge_chip_cfg_init()
[all …]
H A Dbge_main2.c597 (void) bge_check_acc_handle(bgep, bgep->cfg_handle);
604 (void) bge_check_acc_handle(bgep, bgep->cfg_handle);
614 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) {
667 (void) bge_check_acc_handle(bgep, bgep->cfg_handle);
695 (void) bge_check_acc_handle(bgep, bgep->cfg_handle);
716 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) {
1372 bgep->cfg_handle);
1390 bgep->cfg_handle);
1401 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) {
1445 (void) bge_check_acc_handle(bgep, bgep->cfg_handle);
[all …]
/titanic_41/usr/src/uts/i86pc/io/psm/
H A Duppc.c856 ddi_acc_handle_t cfg_handle; in uppc_translate_irq() local
887 if (pci_config_setup(dip, &cfg_handle) != DDI_SUCCESS) in uppc_translate_irq()
890 ipin = pci_config_get8(cfg_handle, PCI_CONF_IPIN) - PCI_INTA; in uppc_translate_irq()
891 iline = pci_config_get8(cfg_handle, PCI_CONF_ILINE); in uppc_translate_irq()
914 pci_config_put8(cfg_handle, in uppc_translate_irq()
917 pci_config_teardown(&cfg_handle); in uppc_translate_irq()
921 pci_config_teardown(&cfg_handle); in uppc_translate_irq()
H A Dpsm_common.c347 ddi_acc_handle_t cfg_handle; in psm_is_pci_bridge() local
350 if (pci_config_setup(dip, &cfg_handle) == DDI_SUCCESS) { in psm_is_pci_bridge()
351 rv = ((pci_config_get8(cfg_handle, PCI_CONF_BASCLASS) == in psm_is_pci_bridge()
352 PCI_CLASS_BRIDGE) && (pci_config_get8(cfg_handle, in psm_is_pci_bridge()
354 pci_config_teardown(&cfg_handle); in psm_is_pci_bridge()
/titanic_41/usr/src/lib/fm/topo/modules/sun4v/hostbridge/
H A Dhb_sun4v.c336 dnode1 = find_dnode(rcs, rcp->cfg_handle); in platform_hb_enum()
379 dnode1 = find_dnode(rcs, rcp->cfg_handle); in platform_hb_enum()
387 hbnode[nhbnode], rcp->id, rcp->cfg_handle); in platform_hb_enum()
H A Dhb_mdesc.h50 uint64_t cfg_handle; /* bus address */ member
H A Dhb_mdesc.c145 hbp->rcs[nrcs].cfg_handle = x; in hb_rc_init()
/titanic_41/usr/src/uts/common/io/rge/
H A Drge_chip.c707 chip->is_pcie = pci_lcap_locate(rgep->cfg_handle, in rge_chip_ident()
730 pci_config_put8(rgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 0x40); in rge_chip_ident()
803 handle = rgep->cfg_handle; in rge_chip_cfg_init()
1767 regval = pci_config_get8(rgep->cfg_handle, regno); in rge_chip_peek_cfg()
1771 regval = pci_config_get16(rgep->cfg_handle, regno); in rge_chip_peek_cfg()
1775 regval = pci_config_get32(rgep->cfg_handle, regno); in rge_chip_peek_cfg()
1779 regval = pci_config_get64(rgep->cfg_handle, regno); in rge_chip_peek_cfg()
1803 pci_config_put8(rgep->cfg_handle, regno, regval); in rge_chip_poke_cfg()
1807 pci_config_put16(rgep->cfg_handle, regno, regval); in rge_chip_poke_cfg()
1811 pci_config_put32(rgep->cfg_handle, regno, regval); in rge_chip_poke_cfg()
[all …]
/titanic_41/usr/src/uts/common/io/nge/
H A Dnge_chip.c125 regval = pci_config_get8(ngep->cfg_handle, regno); in nge_chip_peek_cfg()
129 regval = pci_config_get16(ngep->cfg_handle, regno); in nge_chip_peek_cfg()
133 regval = pci_config_get32(ngep->cfg_handle, regno); in nge_chip_peek_cfg()
137 regval = pci_config_get64(ngep->cfg_handle, regno); in nge_chip_peek_cfg()
162 pci_config_put8(ngep->cfg_handle, regno, regval); in nge_chip_poke_cfg()
166 pci_config_put16(ngep->cfg_handle, regno, regval); in nge_chip_poke_cfg()
170 pci_config_put32(ngep->cfg_handle, regno, regval); in nge_chip_poke_cfg()
174 pci_config_put64(ngep->cfg_handle, regno, regval); in nge_chip_poke_cfg()
600 handle = ngep->cfg_handle; in nge_chip_cfg_init()
1033 pci_config_put8(ngep->cfg_handle, PCI_CONF_CACHE_LINESZ, in nge_chip_reset()
[all …]
/titanic_41/usr/src/uts/common/io/hme/
H A Dhme.c1054 ddi_acc_handle_t cfg_handle; in hmeget_promprops() local
1083 0, 0, &hmep->hme_dev_attr, &cfg_handle)) { in hmeget_promprops()
1090 ddi_put16(cfg_handle, &cfg_ptr->command, in hmeget_promprops()
1097 rom_bar = ddi_get32(cfg_handle, &cfg_ptr->base30); in hmeget_promprops()
1098 ddi_put32(cfg_handle, &cfg_ptr->base30, rom_bar | 1); in hmeget_promprops()
1106 ddi_regs_map_free(&cfg_handle); in hmeget_promprops()
1115 ddi_regs_map_free(&cfg_handle); in hmeget_promprops()
1169 ddi_acc_handle_t cfg_handle; in hmeattach() local
1399 0, 0, &hmep->hme_dev_attr, &cfg_handle)) { in hmeattach()
1407 hm_rev = ddi_get8(cfg_handle, &cfg_ptr->revid); in hmeattach()
[all …]
/titanic_41/usr/src/uts/i86pc/io/
H A Dmp_platform_common.c1358 ddi_acc_handle_t cfg_handle; in apic_handle_pci_pci_bridge() local
1367 (pci_config_setup(dipp, &cfg_handle) != DDI_SUCCESS)) in apic_handle_pci_pci_bridge()
1369 if ((pci_config_get8(cfg_handle, PCI_CONF_BASCLASS) == in apic_handle_pci_pci_bridge()
1370 PCI_CLASS_BRIDGE) && (pci_config_get8(cfg_handle, in apic_handle_pci_pci_bridge()
1372 pci_config_teardown(&cfg_handle); in apic_handle_pci_pci_bridge()
1396 pci_config_teardown(&cfg_handle); in apic_handle_pci_pci_bridge()
/titanic_41/usr/src/uts/common/io/nxge/
H A Dnxge_main.c1962 ddi_acc_handle_t cfg_handle; in nxge_test_map_regs() local
1976 cfg_handle = nxgep->dev_regs->nxge_pciregh; in nxge_test_map_regs()
1986 NXGE_PIO_READ16(cfg_handle, &cfg_ptr->vendorid, 0), in nxge_test_map_regs()
1987 NXGE_PIO_READ16(cfg_handle, &cfg_ptr->devid, 0))); in nxge_test_map_regs()
1991 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base, 0), in nxge_test_map_regs()
1992 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base14, 0), in nxge_test_map_regs()
1993 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base18, 0), in nxge_test_map_regs()
1994 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base1c, 0))); in nxge_test_map_regs()
1998 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base20, 0), in nxge_test_map_regs()
1999 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base24, 0), in nxge_test_map_regs()
[all …]
/titanic_41/usr/src/uts/common/sys/fibre-channel/fca/oce/
H A Doce_impl.h233 ddi_acc_handle_t cfg_handle; /* MMIO PCI Config Space Regs */ member

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