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Searched refs:buffer_mode (Results 1 – 7 of 7) sorted by relevance

/titanic_41/usr/src/uts/common/io/xge/hal/xgehal/
H A Dxgehal-ring.c169 if (ring->buffer_mode == XGE_HAL_RING_QUEUE_BUFFER_MODE_5) { in __hal_ring_mempool_item_alloc()
255 ring->buffer_mode = queue->buffer_mode; in __hal_ring_open()
270 ring->rxd_size = XGE_HAL_RING_RXD_SIZEOF(queue->buffer_mode); in __hal_ring_open()
276 ring->rxds_per_block = XGE_HAL_RING_RXDS_PER_BLOCK(queue->buffer_mode); in __hal_ring_open()
399 xge_assert(queue->buffer_mode == 1 || in __hal_ring_prc_enable()
400 queue->buffer_mode == 3 || in __hal_ring_prc_enable()
401 queue->buffer_mode == 5); in __hal_ring_prc_enable()
424 val64 |= vBIT((queue->buffer_mode >> 1),14,2);/* 1,3 or 5 => 0,1 or 2 */ in __hal_ring_prc_enable()
456 ring->channel.post_qid, queue->buffer_mode); in __hal_ring_prc_enable()
H A Dxgehal-config.c235 if ((new_config->buffer_mode != XGE_HAL_RING_QUEUE_BUFFER_MODE_1) && in __hal_ring_queue_check()
236 (new_config->buffer_mode != XGE_HAL_RING_QUEUE_BUFFER_MODE_3) && in __hal_ring_queue_check()
237 (new_config->buffer_mode != XGE_HAL_RING_QUEUE_BUFFER_MODE_5)) { in __hal_ring_queue_check()
H A Dxgehal-ring-fp.c39 if (ring->buffer_mode == XGE_HAL_RING_QUEUE_BUFFER_MODE_5) { in __hal_ring_rxd_priv()
705 if (ring->buffer_mode == XGE_HAL_RING_QUEUE_BUFFER_MODE_5) { in xge_hal_ring_dtr_next_completed()
825 if (ring->buffer_mode == XGE_HAL_RING_QUEUE_BUFFER_MODE_5) { in xge_hal_ring_is_next_dtr_completed()
H A Dxgehal-mgmtaux.c1630 __HAL_AUX_ENTRY(key, ring->buffer_mode, "%u"); in xge_hal_aux_device_config_read()
/titanic_41/usr/src/uts/common/io/xge/hal/include/
H A Dxgehal-config.h375 int buffer_mode; member
H A Dxgehal-ring.h308 int buffer_mode; member
/titanic_41/usr/src/uts/common/io/xge/drv/
H A Dxge.c309 device_config->ring.queue[index].buffer_mode = in xge_ring_config()