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Searched refs:bmcr (Results 1 – 6 of 6) sorted by relevance

/titanic_41/usr/src/uts/common/io/nxge/
H A Dnxge_mac.c4795 mii_bmcr_t bmcr; in nxge_mii_xcvr_init() local
4830 bmcr.value = 0; in nxge_mii_xcvr_init()
4831 bmcr.bits.reset = 1; in nxge_mii_xcvr_init()
4834 (uint8_t)(uint32_t)&mii_regs->bmcr, in nxge_mii_xcvr_init()
4836 (uint8_t)(uint64_t)&mii_regs->bmcr, in nxge_mii_xcvr_init()
4838 bmcr.value)) != NXGE_OK) in nxge_mii_xcvr_init()
4844 (uint8_t)(uint32_t)&mii_regs->bmcr, in nxge_mii_xcvr_init()
4846 (uint8_t)(uint64_t)&mii_regs->bmcr, in nxge_mii_xcvr_init()
4848 &bmcr.value)) != NXGE_OK) in nxge_mii_xcvr_init()
4851 } while ((bmcr.bits.reset) && (delay < 1000)); in nxge_mii_xcvr_init()
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/titanic_41/usr/src/uts/common/io/mii/
H A Dmii.c1132 uint16_t bmcr, gtcr; in phy_loop() local
1150 bmcr = 0; in phy_loop()
1160 bmcr |= MII_CONTROL_LOOPBACK; in phy_loop()
1163 bmcr |= MII_CONTROL_1GB | MII_CONTROL_FDUPLEX; in phy_loop()
1166 bmcr |= MII_CONTROL_100MB | MII_CONTROL_FDUPLEX; in phy_loop()
1169 bmcr |= MII_CONTROL_FDUPLEX; in phy_loop()
1175 bmcr = MII_CONTROL_FDUPLEX; in phy_loop()
1181 bmcr = MII_CONTROL_100MB | MII_CONTROL_FDUPLEX; in phy_loop()
1187 bmcr = MII_CONTROL_1GB | MII_CONTROL_FDUPLEX; in phy_loop()
1204 phy_write(ph, MII_CONTROL, bmcr); in phy_loop()
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/titanic_41/usr/src/uts/common/io/bfe/
H A Dbfe.c548 uint16_t bmsr, bmcr, anar; in bfe_startup_phy() local
595 bmcr = prog = 0; in bfe_startup_phy()
682 bmcr = (MII_CONTROL_ANE | MII_CONTROL_RSAN); in bfe_startup_phy()
685 bmcr = (MII_CONTROL_100MB | MII_CONTROL_FDUPLEX); in bfe_startup_phy()
687 bmcr = MII_CONTROL_100MB; in bfe_startup_phy()
689 bmcr = MII_CONTROL_FDUPLEX; in bfe_startup_phy()
691 bmcr = 0; /* 10HDX */ in bfe_startup_phy()
697 if (bmcr) in bfe_startup_phy()
698 bfe_write_phy(bfe, MII_CONTROL, bmcr); in bfe_startup_phy()
701 bfe->bfe_mii_bmcr = bmcr; in bfe_startup_phy()
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/titanic_41/usr/src/uts/common/io/mxfe/
H A Dmxfe.c1258 unsigned bmcr; in mxfe_startphymii() local
1336 bmcr = mxfe_miiread(mxfep, phyaddr, MII_CONTROL); in mxfe_startphymii()
1406 bmcr = (MII_CONTROL_ANE | MII_CONTROL_RSAN); in mxfe_startphymii()
1410 bmcr = (MII_CONTROL_100MB | MII_CONTROL_FDUPLEX); in mxfe_startphymii()
1412 bmcr = MII_CONTROL_100MB; in mxfe_startphymii()
1414 bmcr = MII_CONTROL_FDUPLEX; in mxfe_startphymii()
1417 bmcr = 0; in mxfe_startphymii()
1423 DBG(DPHY, "programming bmcr to 0x%x", bmcr); in mxfe_startphymii()
1424 mxfe_miiwrite(mxfep, phyaddr, MII_CONTROL, bmcr); in mxfe_startphymii()
1483 uint16_t bmcr; in mxfe_checklinkmii() local
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/titanic_41/usr/src/uts/common/sys/nxge/
H A Dnxge_mii.h60 uchar_t bmcr; /* Basic mode control register */ member
/titanic_41/usr/src/grub/grub-0.97/netboot/
H A Dtg3.c758 uint32_t aux_stat, bmcr; in tg3_setup_copper_phy() local
771 tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_setup_copper_phy()
772 tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_setup_copper_phy()
773 if (bmcr & BMCR_ANENABLE) { in tg3_setup_copper_phy()